The HC4015 consists of two identical, independent, 4-stage serial-input/parallel-output registers. Each register has independent Clock (CP) and Reset (MR) inputs as well as a single serial Data input. "Q" outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive- going clock transition. Resetting of all stages is accomplished by a high level on the reset line.
The device can drive up to 10 low power Schottky equivalent loads. The HC4015 is an enhanced version of equivalent CMOS types.
|Part number||Order||Technology Family||VCC (Min) (V)||VCC (Max) (V)||Voltage (Nom) (V)||F @ nom voltage (Max) (MHz)||ICC @ nom voltage (Max) (mA)||tpd @ nom Voltage (Max) (ns)||IOL (Max) (mA)||IOH (Max) (mA)||3-state output||Rating||Operating temperature range (C)|
||HC||2||6||6||28||0.08||37||5.2||-5.2||No||Catalog||-55 to 125|
|CD54HC4015||Samples not available||HC||2||6||6||28||0.08||37||5.2||-5.2||No||Military||-55 to 125|