High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs
Product details
Parameters
Package | Pins | Size
Features
- Fully Static Operation
- Buffered Inputs
- Common Reset
- Positive Edge Clocking
- Typical fMAX = 50MHz at VCC =5V,CL = 15pF, TA =25°C
- Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . -55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
Description
The HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE (CE\) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except "0", low.
The device can drive up to 10 low power Schottky equivalent loads.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Reference designs
Design files
-
download TIDA-01027 BOM.pdf (209KB) -
download TIDA-01027 Assembly Drawing.pdf (878KB) -
download TIDA-01027 PCB.pdf (2971KB) -
download TIDA-01027 CAD Files.zip (2870KB) -
download TIDA-01027 Gerber.zip (765KB)
The design has protections, such as load dump through TVS (ISO pulse testing), as well as reverse voltage (innovative smart diode with very low Iq) protection. Furthermore, all the controllers (boost and (...)
Design files
-
download TIDA-00744 BOM.pdf (28KB) -
download TIDA-00744 Gerber.zip (640KB) -
download TIDA-00744 Altium.zip (1537KB)
Design files
-
download PMP10749 BOM.pdf (25KB) -
download PMP10749 Altium.zip (1778KB) -
download PMP10749 Gerber.zip (454KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
PDIP (N) | 16 | View options |
SO (NS) | 16 | View options |
SOIC (D) | 16 | View options |
TSSOP (PW) | 16 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
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