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CD74HC4017

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High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

Data sheet
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High Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs

CD74HC4017

ACTIVE
Data sheet Order now

Product details

Parameters

Function Counter Bits (#) 10 Technology Family HC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other Counter, arithmetic & parity function ICs

Features

  • Fully Static Operation
  • Buffered Inputs
  • Common Reset
  • Positive Edge Clocking
  • Typical fMAX = 50MHz at VCC =5V,CL = 15pF, TA =25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V

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Description

The ’HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the decoded outputs is normally low and sequentially goes high on the low to high transition clock period of the 10 clock period cycle. The CARRY (TC) output transitions low to high after OUTPUT 10 goes low, and can be used in conjunction with the CLOCK ENABLE (CE\) to cascade several stages. The CLOCK ENABLE input disables counting when in the high state. A RESET (MR) input is also provided which when taken high sets all the decoded outputs, except "0", low.

The device can drive up to 10 low power Schottky equivalent loads.

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Technical documentation

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Type Title Date
* Data sheet CD54HC4017/CD74HC4017 High-Speed CMOS Logic Decade Counter/Divider datasheet (Rev. D) Oct. 16, 2003
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details

Reference designs

REFERENCE DESIGNS Download
Low noise power-supply reference design maximizing performance in 12.8 GSPS data acquisition systems
TIDA-01027 — This reference design demonstrates an efficient, low noise 5-rail power-supply design for very high-speed DAQ systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency synchronized and phase-shifted in order to minimize input current ripple and control frequency content (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
50W System-Level Power Reference Design for Automotive Infotainment Systems
TIDA-00744 — TIDA-00744 is a 50-W system-level SMPS design for mid-power automotive infotainment systems.
The design has protections, such as load dump through TVS (ISO pulse testing), as well as reverse voltage (innovative smart diode with very low Iq) protection. Furthermore, all the controllers (boost and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
100W System-Level Power Reference Design for Automotive Infotainment System
PMP10749 — PMP10749 is a 100-W system-level SMPS design for a higher-power automotive infotainment system. The design has protections, such as load dump through TVS (ISO pulse testing), as well as reverse voltage (innovative smart diode with very low Iq) protection. Furthermore, all the controllers (boost and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
SOIC (D) 16 View options
TSSOP (PW) 16 View options

Ordering & quality

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