CD74HC4094

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High Speed CMOS Logic 8-Stage Shift-and-Store Bus Register with 3-Stage Outputs

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Product details

Parameters

Configuration Serial-in, Parallel-out Bits (#) 8 Technology Family HC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Input type Standard CMOS Output type 3-State Clock Frequency (MHz) 24 IOL (Max) (mA) 5.2 IOH (Max) (mA) -5.2 ICC (Max) (uA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Output register open-in-new Find other Shift register

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 TSSOP (PW) 16 22 mm² 4.4 x 5 TSSOP (PW) 16 22 mm² 5 x 4.4 open-in-new Find other Shift register

Features

  • Buffered Inputs
  • Separate Serial Outputs Synchronous to Both
    Positive and Negative Clock Edges For Cascading
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . .–55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL
    Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC
      at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility,
      VIL= 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH

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Description

The ’HC4094and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered three-stateoutputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.

Two serial outputs are available for cascading a number of these devices. Data is available at the QS1 serial output terminal on positive clock edges to allow for high-speed operation in cascaded system in which the clock rise time is fast. The same serial information, available at the QS2 terminal on the next negative clock edge, provides a means for cascading these devices when the clock rise time is slow.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet CD54HC4094, CD74HC4094, CD74HCT4094 datasheet (Rev. E) Jan. 01, 2011
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
SOIC (D) 16 View options
TSSOP (PW) 16 View options

Ordering & quality

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