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CD74HC4094

ACTIVE

High speed CMOS Logic 8-stage shift-and-store bus register with 3-stage outputs

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Data sheet

CD74HC4094

ACTIVE
Data sheet Order now

Product details

Configuration Serial-in Bits (#) 8 Technology family HC Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
Configuration Serial-in Bits (#) 8 Technology family HC Input type Standard CMOS Output type 3-State Clock frequency (MHz) 24 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Output register, Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm) TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) SOT-23-THN (DYY) 16 8.4 mm² (4.2 mm × 2 mm)
  • Buffered inputs
  • Separate serial outputs synchronous to both positive and negative clock edges for cascading
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temp range: −55°C to 125°C
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL logic ICs
  • HC types
    • 2- to 6-V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5- to 5.5-V operation
    • Direct LSTTL input logic compatibility, VIL= 0.8 V (Max), VIH = 2 V (Min)
    • CMOS input compatibility, Il ≤ 1µA at VOL, VOH
  • Buffered inputs
  • Separate serial outputs synchronous to both positive and negative clock edges for cascading
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temp range: −55°C to 125°C
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL logic ICs
  • HC types
    • 2- to 6-V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5- to 5.5-V operation
    • Direct LSTTL input logic compatibility, VIL= 0.8 V (Max), VIH = 2 V (Min)
    • CMOS input compatibility, Il ≤ 1µA at VOL, VOH

The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.

The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high.
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CD74HCT4094 ACTIVE High Speed CMOS Logic 8-Stage Shift-and-Store Bus Register with 3-Stage Outputs Voltage range 4.5V to 5.5V, average propagation delay 22ns, average drive strength 4mA

Technical documentation

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* Data sheet CDx4HC4094, CD74HCT4094 High-Speed CMOS Logic 8-Stage Shift and Store Bus Register, Three-State datasheet (Rev. F) PDF | HTML Nov 24, 1998
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Package Pins CAD symbols, footprints & 3D models
PDIP (N) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
SOT-23-THN (DYY) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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