CD74HC573 High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs | TI.com

CD74HC573
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High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs

High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs - CD74HC573
Datasheet
 

Description

The 'HC573 devices are octal transparent D-type latches designed for 2-V to 6-V VCC operation.

When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Features

  • 2-V to 6-V VCC Operation
  • Wide Operating Temperature Range of –55°C to 125°C
  • 3-State Outputs Directly Drive Bus Lines
  • Balanced Propagation Delays and Transition Times
  • Bus Driver Outputs Drive Up To 15 LS-TTL Loads
  • Significant Power Reduction Compared to LS-TTL Logic ICs

Parametrics

Compare all products in D-type latch Email Download to Excel
Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) IOL (Max) (mA) IOH (Max) (mA) Rating Package Group
CD74HC573 Order now HC     CMOS     CMOS     2     6     7.8     -7.8     Catalog     PDIP | 20
SOIC | 20    
CD54HC573 Samples not available HC     CMOS     CMOS     2     6     7.8     -7.8     Military     CDIP | 20