CD74HC74

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High Speed CMOS Logic Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset

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Product details

Parameters

Channels (#) 2 Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 28 IOL (Max) (mA) 5.2 IOH (Max) (mA) -5.2 ICC (Max) (uA) 40 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode open-in-new Find other D-type flip-flop

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 open-in-new Find other D-type flip-flop

Features

  • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
  • Asynchronous Set and Reset
  • Complementary Outputs
  • Buffered Inputs
  • Typical fMAX = 50MHz at VCC = 5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

open-in-new Find other D-type flip-flop

Description

The ’HC74 and ’HCT74 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.

This flip-flop has independent DATA, SET\, RESET\ and CLOCK inputs and Q and Q\ outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. SET\ and RESET\ are independent of the clock and are accomplished by a low level at the appropriate input.

The HCT logic family is functionally as well as pin compatible with the standard LS logic family.

open-in-new Find other D-type flip-flop
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 16
Type Title Date
* Datasheet CDx4HC74, CDx4HCT74 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger datasheet (Rev. D) Aug. 21, 2003
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Reference designs

REFERENCE DESIGNS Download
Highly Efficient, 1.6kW High Density GaN Based 1MHz CrM Totem-pole PFC Converter Reference Design
TIDA-00961 — High frequency Critical-Conduction-Mode (CrM) Totem-pole power factor correction (PFC) is a simple approach for designing high density power solutions using GaN.  The TIDA-0961 reference design uses TI’s 600V GaN power stage, LMG3410, and TI’s Piccolo™ F280049 controller. This (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options

Ordering & quality

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