CDC7005

ACTIVE

High performance, low phase noise, low skew clock synchronizer that synchronizes ref clock to VCXO

Top

Product details

Parameters

Function Clock generator Number of outputs 5 Output frequency (Max) (MHz) 800 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVCMOS, LVPECL Output type LVPECL Operating temperature range (C) -40 to 85 Features Op-amp for active loop filter, Programmable delay Rating Catalog open-in-new Find other Clock generators

Package | Pins | Size

BGA (ZVA) 64 64 mm² 8 x 8 VQFN (RGZ) 48 49 mm² 7.0 x 7.0 open-in-new Find other Clock generators

Features

  • High Performance 1:5 PLL Clock Synchronizer
  • Two Clock Inputs: VCXO_IN Clock Is Synchronized to REF_IN Clock
  • Synchronizes Frequencies up to 800 MHz (VCXO_IN)
  • Supports Five Differential LVPECL Outputs
  • Each Output Frequency Is Selectable by x1, /2, /4, /8, /16
  • All Outputs Are Synchronized
  • Integrated Low-Noise OPA for External Low-Pass Filter
  • Efficient Jitter Screening From Low PLL Loop Bandwidth
  • Low-Phase Noise Characteristic
  • Programmable Delay for Phase Adjustments
  • Predivider Loop BW Adjustment
  • SPI Controllable Division Setting
  • Power-Up Control Forces LVPECL Outputs to 3-State at VCC <1.5 V
  • 3.3-V Power Supply
  • Packaged In 64-Pin BGA (0,8 mm Pitch - ZVA) or 48-Pin QFN (RGZ)
  • Industrial Temperature Range –40°C to 85°C

open-in-new Find other Clock generators

Description

The CDC7005 is a high-performance, low-phase noise, and low-skew clock synchronizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO: VCXO_IN/REF_IN = (NxP)/M. The VCXO_IN clock operates up to 800 MHz. Through the selection of external VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different system requirements. Each of the five differential LVPECL outputs is programmable by the serial peripheral interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.

The CDC7005 is characterized for operation from –40°C to 85°C.

open-in-new Find other Clock generators
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 20
Type Title Date
* Data sheet 3.3-V High Performance Clock Synthesizer & Jitter Cleaner datasheet (Rev. L) Jun. 04, 2009
Technical article How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
Technical article Clocking sampled systems to minimize jitter Jul. 31, 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014
Application note Using The CDC7005 as a 1:5 PECL Buffer w/Programmable Divider Ratio (Rev. B) Dec. 15, 2009
Application note Basics of the CDC7005 Hold Function Apr. 13, 2006
User guide CDC7005 (BGA Package) EVM (Rev. E) Mar. 28, 2006
User guide CDC7005 (QFN Package) Evaluation Module Manual (Rev. B) Mar. 28, 2006
User guide CDC7005 (BGA Package) EVM (Rev. D) Dec. 29, 2005
User guide CDC7005 (QFN Package) Evaluation Module Manual (Rev. A) Dec. 29, 2005
User guide CDC7005 (QFN Package) Evaluation Module Manual Jul. 20, 2005
Application note Phase Noise (Jitter) Performance of CDC7005 With Different VCXOs (Rev. A) Jul. 19, 2005
User guide CDC7005EVM User Guide (Rev. C) Feb. 17, 2005
Application note Open Loop Phase-Noise Performance of CDC7005 at Various Frequencies Dec. 17, 2004
User guide TSW2000 Receive Clock JItter Cleaning EVM Jun. 28, 2004
Application note Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC Dev Jun. 25, 2004
More literature ADS5500 + CDC7005 Product Bulletin Jun. 23, 2004
More literature TSW2000: TLK1201A & CDC7005 Jun. 23, 2004
Application note General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner (Rev. A) Dec. 16, 2003
Application note General Guidelines: CDC7005 as a Clock Synthesizer and Jitter Cleaner Mar. 21, 2003

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
199
Description

The CDC7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates very low phase noise (jitter) clock.

The PLL loop bandwidth and damping factor can be adjusted to meet (...)

Features
  • Operates up to 800 MHz
  • Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
  • Can be used as a simple 1:5 LVPECL buffer with output dividing options
  • Differential outputs programmable by serial peripheral interface (SPI)
EVALUATION BOARD Download
document-generic User guide
199
Description

The CDC7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates very low phase noise (jitter) clock.

The PLL loop bandwidth and damping factor can be adjusted to meet (...)

Features
  • Operates up to 800 MHz
  • Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
  • Can be used as a simple 1:5 LVPECL buffer with output dividing options
  • Differential outputs programmable by serial peripheral interface (SPI)
EVALUATION BOARD Download
document-generic User guide
199
Description

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates very low phase noise (jitter) clock.

The PLL loop bandwidth and damping factor can be adjusted to meet (...)

Features
  • Output frequency up to 1500 MHz
  • Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
  • Can be used as a simple 1:5 LVPECL buffer with output dividing options
  • Differential outputs programmable by serial peripheral interface (SPI)
EVALUATION BOARD Download
document-generic User guide
199
Description

TheCDCM7005QFN-EVM is an evaluation module designed to aid in evaluating the performance of the CDCM7005, which is a high-performance, low phase noise and low skew clock synchronizer that synchronizes voltage controlled crystal oscillator (VCXO) frequency to an external reference clock; generates (...)

Features
  • Output frequency up to 1500 MHz
  • Loop bandwidth can be selected as low as 10 Hz or less to clean the system's clock jitter
  • Can be used as a simple 1:5 LVPECL buffer with output dividing options
  • Differential outputs programmable by serial peripheral interface (SPI)

Software development

SUPPORT SOFTWARE Download
SCAC037A.ZIP (55329 KB)

Design tools & simulation

SIMULATION MODEL Download
SCAC033.ZIP (34 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
CALCULATION TOOL Download
CDC7005 and CDCM7005 PLL Loop Bandwidth Calculator
CDC-CDCM7005-CALC This tool helps to determine the right divider values (M, N & P) and to choose the filter type and components. This calculator will help to find out the appropriate loop bandwidth, phase margin, jitter peaking, etc. just varying the loop parameters like PFD frequency, filter components, Charge pump (...)
Features

The lab view based tool can:

  • Determine the PFD frequency automatically
  • Calculate loop bandwidth, Phase margin and Jitter peaking
  • Predict the PLL output Phase noise
  • Calculate Phase Jitter (rms)
BILL OF MATERIALS (BOM) Download
SLWR028.ZIP (166 KB)
GERBER FILE Download
SCAC066.ZIP (537 KB)
GERBER FILE Download
SLWC050.ZIP (532 KB)

CAD/CAE symbols

Package Pins Download
BGA (ZVA) 64 View options
VQFN (RGZ) 48 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos