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Product details

Parameters

Function Binary Counter Bits (#) 4 Technology Family FCT VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

SOIC (DW) 16 77 mm² 7.52 x 10.28 SSOP (DBQ) 16 29 mm² 4.9 x 6 open-in-new Find other Counter, arithmetic & parity function ICs

Features

  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Matched Rise and Fall Times
  • 64-mA Output Sink Current
    32-mA Output Source Current

open-in-new Find other Counter, arithmetic & parity function ICs

Description

The CY74FCT191T is a reversible modulo-16 binary counter, featuring synchronous counting and asynchronous presetting. The preset allows the CY74FCT191T to be used in programmable dividers. The count enable input, terminal count output, and ripple-clock output make possible a variety of methods of implementing multiusage counters. In the counting modes, state changes are initiated by the rising edge of the clock.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

open-in-new Find other Counter, arithmetic & parity function ICs
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet 4-Bit Up/Down Binary Counter datasheet (Rev. A) Sep. 01, 2001
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides CYFCT Parameter Measurement Information Apr. 02, 2001
Selection guides Advanced Bus Interface Logic Selection Guide Jan. 09, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (DW) 16 View options
SSOP (DBQ) 16 View options

Ordering & quality

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