Octal Transparent D-Type Latches with 3-State Outputs
Product details
Parameters
Package | Pins | Size
Features
- Function and Pinout Compatible With FCT and F Logic
- Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
- Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
- Ioff Supports Partial-Power-Down Mode Operation
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Matched Rise and Fall Times
- Fully Compatible With TTL Input and Output Logic Levels
- 3-State Outputs
- CY54FCT373T
- 32-mA Output Sink Current
- 12-mA Output Source Current
- CY74FCT373T
- 64-mA Output Sink Current
- 32-mA Output Source Current
Description
The \x92FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | 8-Bit Latches datasheet (Rev. B) | Aug. 20, 2001 |
Selection guide | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Dec. 02, 2015 | |
Application note | Power-Up Behavior of Clocked Devices (Rev. A) | Feb. 06, 2015 | |
User guide | LOGIC Pocket Data Book (Rev. B) | Jan. 16, 2007 | |
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 | |
Application note | Selecting the Right Level Translation Solution (Rev. A) | Jun. 22, 2004 | |
More literature | Logic Cross-Reference (Rev. A) | Oct. 07, 2003 | |
User guide | CYFCT Parameter Measurement Information | Apr. 02, 2001 | |
Selection guide | Advanced Bus Interface Logic Selection Guide | Jan. 09, 2001 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (DW) | 20 | View options |
SSOP (DBQ) | 20 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.