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CY74FCT373T

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Octal Transparent D-Type Latches with 3-State Outputs

Data sheet
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Octal Transparent D-Type Latches with 3-State Outputs

CY74FCT373T

ACTIVE
Data sheet Order now

Product details

Parameters

Channels (#) 8 Technology Family FCT VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Input type TTL-Compatible CMOS Output type 3-State Clock Frequency (Max) (MHz) 70 IOL (Max) (mA) 64 IOH (Max) (mA) -32 ICC (Max) (uA) 200 Features Very high speed (tpd 5-10ns), Partial power down (Ioff) open-in-new Find other D-type latch

Package | Pins | Size

SOIC (DW) 20 132 mm² 12.8 x 10.3 SSOP (DBQ) 20 52 mm² 8.65 x 6 open-in-new Find other D-type latch

Features

  • Function and Pinout Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • 3-State Outputs
  • CY54FCT373T
    • 32-mA Output Sink Current
    • 12-mA Output Source Current
  • CY74FCT373T
    • 64-mA Output Sink Current
    • 32-mA Output Source Current

 open-in-new Find other D-type latch

Description

The \x92FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

 open-in-new Find other D-type latch
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 10
Type Title Date
* Datasheet 8-Bit Latches datasheet (Rev. B) Aug. 20, 2001
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guide CYFCT Parameter Measurement Information Apr. 02, 2001
Selection guide Advanced Bus Interface Logic Selection Guide Jan. 09, 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details

CAD/CAE symbols

Package Pins Download
SOIC (DW) 20 View options
SSOP (DBQ) 20 View options

Ordering & quality

Information included:
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  • REACH
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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

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