This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT825T is an 8-bit
buffered register with all the CY74FCT823T controls, plus multiple enables (OE\1, OE\2, OE\3) to allow multiuser
control of the interface, e.g., CS\, DMA, and RD/WR\. This device is ideal for use as an output port requiring high
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading
at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.