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Product details

Parameters

Type Mux Buffer Number of channels (#) 4 Input compatibility AC-coupling Speed (Max) (Gbps) 10.3125 Protocols 10G-SR/LR, 40G-SR4-LR4, PCIe1, PCIe2, PCIe3, FibreChannel, Infiniband, Interlaken, sRIO, CPRI, OBSAI, General Purpose Operating temperature range (C) -40 to 85 open-in-new Find other Ethernet retimers, redrivers & mux-buffers

Package | Pins | Size

WQFN (NJY) 54 55 mm² 10 x 5.5 open-in-new Find other Ethernet retimers, redrivers & mux-buffers

Features

  • 10.3125 Gbps Dual Lane 2:1 Mux, 1:2 Switch or
    Fan-Out
  • Low 390 mW Total Power (Typical)
  • Advanced Signal Conditioning Features:
    • Receive Equalization Up to 36 dB at 5 GHz
    • Transmit De-Emphasis Up to –12 dB
    • Transmit Output Voltage Control: 600 mV to
      1300 mV
  • Programmable Through Pin Selection, EEPROM
    or SMBus Interface
  • Selectable 2.5-V or 3.3-V Supply Voltage
  • –40°C to 85°C Operating Temperature Range
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Description

The DS100MB203 device is a dual port 2:1 multiplexer and 1:2 switch or fan-out buffer with signal conditioning suitable for 10GE, 10G-KR (802.3ap), Fibre Channel, PCIe, Infiniband, SATA3/SAS2 and other high-speed bus applications with data rates up to 10.3125 Gbps.

The continuous time linear equalizer (CTLE) of the receiver provides necessary boost to compensate up to 40” FR-4 or 10m cable (AWG-24) at 10.3125 Gbps - This on-chip feature eliminates the need for external signal conditioners. The transmitter features a programmable amplitude voltage levels to be selectable from 600 mVp-p to 1300 mVp-p and De-Emphasis of up to 12 dB.

The DS100MB203 can be configured to support PCIe, SAS/SATA, 10G-KR or other signaling protocols. When operating in 10G-KR and PCIe Gen-3 mode, the DS100MB203 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients. This seamless management of the link training protocol ensures system level interoperability with minimum latency.

The programmable settings can be applied through pin settings, SMBus (I2C) protocol or loaded directly from an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power up, which eliminates the need for an external microprocessor or software driver.

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Technical documentation

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Type Title Date
* Data sheet DS100MB203 10.3125 Gbps Dual Lane 2:1/1:2 Mux/Buffer With Equalization and De-Emphasis datasheet (Rev. D) Jan. 19, 2016
Application note Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications May 15, 2020
Application note Understanding EEPROM Programming for High Speed Repeaters and Mux Buffers Oct. 09, 2014
User guide DS100MB203EVK User's Guide Oct. 17, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
499
Description

The DS100MB203EVK is a dual Lane 2:1/1:2 Mux/Buffer SMA evaluation kit. It provides a complete high bandwidth platform to evaluate the signal integrity and signal conditioning features of the DS100MB203SQ – 10.3125 Gbps Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis.

Features
  • 10.3125 Gbps Dual Lane 2:1 Mux, 1:2 Switch or Fanout
  • Low 390 mW total power (typ) power consumption, with option to power down unused channels
  • Advanced signal conditioning features
    • Receive Equalization up to 36 dB at 5 GHz
    • Transmit de-emphasis up to -12 dB
    • Transmit output voltage control: 600 mV to 1300 (...)

Design tools & simulation

SIMULATION MODEL Download
SNLM143.PDF (25 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
WQFN (NJY) 54 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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