Product details

Type Retimer Number of channels (#) 4 Input compatibility AC-coupling, CML Speed (Max) (Gbps) 11.3 Protocols 10G-SR/LR, 40G-SR4/LR4, Infiniband, General purpose Operating temperature range (C) -40 to 85
Type Retimer Number of channels (#) 4 Input compatibility AC-coupling, CML Speed (Max) (Gbps) 11.3 Protocols 10G-SR/LR, 40G-SR4/LR4, Infiniband, General purpose Operating temperature range (C) -40 to 85
WQFN (RHS) 48 49 mm² 7 x 7
  • Each Channel Independently Locks to Data Rates
    from 8.5 to 11.3 Gbps and Sub-rates
  • Sub-rates of Divide by 2, 4, or 8
  • Fast-Lock Operation Based on Protocol-Select
    Mode
  • Low Latency (≈ 300 ps)
  • Adaptive Equalization up to 34-dB Boost at 5 GHz
  • Adjustable Transmit VOD: 600 to 1300 mVp-p
  • Adjustable Transmit De-emphasis to –12 dB
  • Typical Power Dissipation (EQ+CDR+DE):
    150 mW/Channel
  • Programmable Output Polarity Inversion
  • Input Signal Detection, CDR Lock Detection and
    Indicator
  • On-Chip Eye Monitor (EOM), PRBS Generator
  • Single 2.5-V ±5% Power Supply
  • SMBus and EEPROM Configuration Modes
  • Operating Temperature Range of –40 to 85°C
  • WQFN 48-Pin 7-mm × 7-mm Package
  • Easy Pin Compatible Upgrade Between Repeater
    and Retimers
    • DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
    • DS100DF410 (EQ+DFE+CDR+DE):
      10.3125 Gbps
    • DS110RT410 (EQ+CDR+DE): 8.5 to
      11.3 Gbps
    • DS110DF410 (EQ+DFE+CDR+DE): 8.5 to
      11.3 Gbps
    • DS125RT410 (EQ+CDR+DE): 9.8 to
      12.5 Gbps
    • DS125DF410 (EQ+DFE+CDR+DE):
      9.8 to 12.5 Gbps
    • DS100BR410 (EQ+DE): Up to
      10.3125 Gbps
  • Each Channel Independently Locks to Data Rates
    from 8.5 to 11.3 Gbps and Sub-rates
  • Sub-rates of Divide by 2, 4, or 8
  • Fast-Lock Operation Based on Protocol-Select
    Mode
  • Low Latency (≈ 300 ps)
  • Adaptive Equalization up to 34-dB Boost at 5 GHz
  • Adjustable Transmit VOD: 600 to 1300 mVp-p
  • Adjustable Transmit De-emphasis to –12 dB
  • Typical Power Dissipation (EQ+CDR+DE):
    150 mW/Channel
  • Programmable Output Polarity Inversion
  • Input Signal Detection, CDR Lock Detection and
    Indicator
  • On-Chip Eye Monitor (EOM), PRBS Generator
  • Single 2.5-V ±5% Power Supply
  • SMBus and EEPROM Configuration Modes
  • Operating Temperature Range of –40 to 85°C
  • WQFN 48-Pin 7-mm × 7-mm Package
  • Easy Pin Compatible Upgrade Between Repeater
    and Retimers
    • DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
    • DS100DF410 (EQ+DFE+CDR+DE):
      10.3125 Gbps
    • DS110RT410 (EQ+CDR+DE): 8.5 to
      11.3 Gbps
    • DS110DF410 (EQ+DFE+CDR+DE): 8.5 to
      11.3 Gbps
    • DS125RT410 (EQ+CDR+DE): 9.8 to
      12.5 Gbps
    • DS125DF410 (EQ+DFE+CDR+DE):
      9.8 to 12.5 Gbps
    • DS100BR410 (EQ+DE): Up to
      10.3125 Gbps

The DS110RT410 is a four-channel retimer with integrated signal conditioning. The device includes a fully adaptive continuous-time linear equalizer (CTLE), clock and data recovery (CDR), and a transmit de-emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1 × 10–15. For channels with a high amount of crosstalk, the DS110DF410 should be used because it has self-calibrating 5-tap decision-feedback equalizer (DFE).

Each channel can independently lock to data rates from 8.5 to 11.3 Gbps, and associated sub-rates (divide by 2, 4, and 8) to support a variety of communication protocols. A 25-MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.

The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded through an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning.

The DS110RT410 is a four-channel retimer with integrated signal conditioning. The device includes a fully adaptive continuous-time linear equalizer (CTLE), clock and data recovery (CDR), and a transmit de-emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1 × 10–15. For channels with a high amount of crosstalk, the DS110DF410 should be used because it has self-calibrating 5-tap decision-feedback equalizer (DFE).

Each channel can independently lock to data rates from 8.5 to 11.3 Gbps, and associated sub-rates (divide by 2, 4, and 8) to support a variety of communication protocols. A 25-MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.

The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded through an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning.

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Technical documentation

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Type Title Date
* Data sheet DS110RT410 Low-Power Multi-Rate Quad Channel Retimer datasheet (Rev. A) PDF | HTML 27 Oct 2015
EVM User's guide DS100DF410EVK, DS110DF410EVK, DS125DF410EVM User's Guide (Rev. C) 22 Jun 2016
Application note Understanding EEPROM Programming for 10G to 12.5G Retimers 13 Jan 2016
Application note Selecting TI SigCon Devices for SFF-8431 SFP+ Applications 06 May 2014

Design & development

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Evaluation board

DS110DF410EVM — DS110DF410EVM: 8.5 to 11.3 Gbps Quad Channel Retimer with Adaptive EQ, CDR and DFE Evaluation Module

The DS110DF410EVM evaluation board allows the user to examine the advanced signal conditioning capabilities of the DS110DF410 and DS110RT410 devices using SMAs. The board is controlled by a PC using a USB port and the SigCon Architect GUI.

In order to use the SigCon Architect GUI to control the (...)

User guide: PDF
Not available on TI.com
Simulation model

IBIS-AMI Model Request Form

SNLM143.PDF (25 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
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WQFN (RHS) 48 View options

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