Product details


Type Retimer Mux Number of channels (#) 2 Input compatibility AC-coupling, CML Speed (Max) (Gbps) 25.8 Protocols IEEE802.3bj, 100GbE, Infiniband EDR, OIF-CEi-25G-LR/MR/SR/VSR, QSFP28, CFP2/CFP4, CDFP Operating temperature range (C) -40 to 85 open-in-new Find other Ethernet retimers, redrivers & mux-buffers

Package | Pins | Size

FC/CSP (ABM) 101 36 mm² 6 x 6 open-in-new Find other Ethernet retimers, redrivers & mux-buffers


  • Dual-channel multi-rate retimer with integrated signal conditioning
  • All channels lock independently from 20.6 to 25.8 Gbps (including sub-rates such as 10.3125 Gbps, 12.5 Gbps, and more)
  • Ultra-low latency: <500 ps Typical for 25.78125-Gbps data rate
  • Single power supply, no low-jitter reference clock required, and minimal supply decoupling to reduce board routing complexity and BOM cost
  • Adaptive Continuous Time Linear Equalizer (CTLE)
  • Adaptive Decision Feedback Equalizer (DFE)
  • Integrated 2 x 2 cross point
  • Low-jitter transmitter with 3-Tap FIR filter
  • Combined equalization supporting 35+ dB channel loss at 12.9 GHz
  • Adjustable transmit amplitude: 205 mVppd to 1225 mVppd (typical)
  • On-Chip Eye Opening Monitor (EOM), PRBS pattern checker and generator
  • Small 6-mm × 6-mm BGA package with easy flow-through routing
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The DS250DF210 device is a two-channel, multi-rate retimer with integrated signal conditioning. It is used to extend the reach and robustness of long, lossy, crosstalk-impaired, high-speed serial links while achieving a bit error rate (BER) of 10-15 or less.

Each channel of the DS250DF210 independently locks to serial data rates in a continuous range from 20.6 Gbps to 25.8 Gbps or to any supported sub-rate (÷2 and ÷4), including key data rates such as 10.3125 Gbps and 12.5 Gbps, which allows the DS250DF210 to support individual lane Forward Error Correction (FEC) pass-through.

The DS250DF210 has a single power supply and minimal need for external components. These features reduce PCB-routing complexity and BOM cost.

The advanced equalization features of the DS250DF210 include a low-jitter 3-tap transmit finite impulse response (FIR) filter, an adaptive continuous-time linear equalizer (CTLE), and an adaptive decision feedback equalizer (DFE). This enables reach extension for lossy interconnect and backplanes with multiple connectors and crosstalk. The integrated CDR function is ideal for front-port optical module applications to reset the jitter budget and retime the high-speed serial data. The DS250DF210 implements a 2x2 cross-point, providing the host with lane crossing, fanout, and multiplexing options

The DS250DF210 can be configured either through the SMBus or through an external EEPROM. Up to 16 devices can share a single EEPROM using Common Channel format. A non-disruptive, on-chip eye monitor and a PRBS generator or checker allow for in-system diagnostics.

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More Information

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Technical documentation

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Type Title Date
* Data sheet DS250DF210 25-Gbps Multi-Rate 2-Channel Retimer datasheet (Rev. B) Oct. 24, 2019
Application note Optimal Implementation of 25G-28G Ethernet Retimers versus Redrivers (Rev. A) Jan. 07, 2020

Design & development

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Hardware development

document-generic User guide

The DS250DF410EVM allows for easy evaluation of the 25 Gbps retimer DS250DF410. Users are required to supply power and high speed traffic to the EVM via Huber+Suhner 1x8 MXP connectors. Huber+Suhner cables are not included.

Through the onboard USB2ANY connection and EVM software, users can evaluate (...)

  • Programmable via on board USB2ANY and EVM software
  • Supports data rates up to 25.8Gbps
  • EVM supports single supply (2.5V or 3.3V)

Design tools & simulation

PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

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FC/CSP (ABM) 101 View options

Ordering & quality

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