DS25BR120

ACTIVE

3.125-Gbps LVDS buffer with transmit pre-emphasis

Product details

Function Buffer Protocols LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 3125 Input signal CML, LVCMOS, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer Protocols LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 3125 Input signal CML, LVCMOS, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
WSON (NGQ) 8 9 mm² 3 x 3
  • DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
  • Four Levels of Transmit Pre-Emphasis Drive Lossy Backplanes and Cables
  • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space
  • 7 kV ESD on LVDS I/O pins Protects Adjoining Components
  • Small 3 mm x 3 mm 8-WSON Space Saving Package

All trademarks are the property of their respective owners.

  • DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
  • Four Levels of Transmit Pre-Emphasis Drive Lossy Backplanes and Cables
  • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space
  • 7 kV ESD on LVDS I/O pins Protects Adjoining Components
  • Small 3 mm x 3 mm 8-WSON Space Saving Package

All trademarks are the property of their respective owners.

The DS25BR120 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

The DS25BR120 features four levels of pre-emphasis (PE) for use as an optimized driver device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR110 features four levels of equalization for use as an optimized receiver device, while the DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.

Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count and further minimize board space.

The DS25BR120 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

The DS25BR120 features four levels of pre-emphasis (PE) for use as an optimized driver device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR110 features four levels of equalization for use as an optimized receiver device, while the DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.

Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count and further minimize board space.

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Technical documentation

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Type Title Date
* Data sheet DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis datasheet (Rev. E) 14 Apr 2013
Application note Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls 29 Oct 2020
Application note Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners 29 Jun 2019
Application note LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) 29 Apr 2013
Application note AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A) 26 Apr 2013
User guide 3.125 Gbps LVDS Buffers with Pre-emphasis and Equalization User Guide 25 Jan 2012

Design & development

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Evaluation board

DS25BR100EVK — 3.125 Gbps LVDS Single Channel Buffers with Transmit Pre-emphasis and Receive Equalization family

The DS25BR100EVK is an evaluation kit designed for demonstrating performance of the 3.125 Gbps LVDS Single Channel Buffers with Transmit Pre-Emphasis (PE) and Receive Equalization (EQ) family (DS25BR100, DS25BR110 and DS25BR120). The evaluation kit provides all three devices on a single board and (...)

User guide: PDF
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Simulation model

DS25BR120 IBIS Model

SNLM098.ZIP (12 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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WSON (NGQ) 8 Ultra Librarian

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