Product details


Function Crosspoint, Equalizer Protocols LVDS, LVPECL, CML Number of Tx 4 Number of Rx 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 3125 Input signal LVDS, LVPECL, CML Output signal LVDS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

WQFN (RTA) 40 36 mm² 6 x 6 open-in-new Find other LVDS, M-LVDS & PECL ICs


  • DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation
  • Pin and SMBus Configurable, Fully Differential, Non-Blocking Architecture
  • Pin (Two Levels) and SMBus (Four Levels) Selectable Pre-Emphasis and Equalization Eliminate ISI Jitter
  • Wide Input Common Mode Range Enables Easy Interface to CML and LVPECL Drivers
  • LOS Circuitry Detects Open Inputs Fault Condition
  • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, Minimizes Board Space The DS25CP114 Eliminates the On-Chip Input Termination for Added Design Flexibility.
  • 8 kV ESD on LVDS I/O Pins Protects Adjoining Components
  • Small 6 mm x 6 mm WQFN-40 Space Saving Package

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Technical documentation

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Type Title Date
* Datasheet DS25CP104A/CP114 3.125 Gbps 4x4 LVDS Xpoint Sw w/Xmit Pre-Emp & Receive Equal datasheet (Rev. C) Mar. 04, 2013
Selection guides Broadcast and Professional Video Interface Solutions (Rev. E) Apr. 05, 2017
Application notes LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) Apr. 29, 2013
Application notes AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A) Apr. 26, 2013
Application notes Triple Rate SDI IP FPGA Resource Utilization on SDXILEVK/AES-EXP-SDI-G Ref Dsgn (Rev. A) Apr. 26, 2013
User guides 3.125 Gbps 4x4 LVDS Crosspoint Switch Evaluation Board Jan. 25, 2012
Application notes DS25CP104 in 3G SDI Router Application Aug. 20, 2008
Application notes A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video Mar. 18, 2008

Design & development

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Design tools & simulation

SNLM065.ZIP (20 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

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WQFN (RTA) 40 View options

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