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Product details

Parameters

Function Crosspoint, Equalizer Protocols LVDS, LVPECL, CML Number of Tx 4 Number of Rx 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 3125 Input signal LVDS, LVPECL, CML Output signal LVDS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

WQFN (RTA) 40 36 mm² 6 x 6 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • DC - 3.125 Gbps Low Jitter, Low Skew, Low Power Operation
  • Pin and SMBus Configurable, Fully Differential, Non-Blocking Architecture
  • Pin (Two Levels) and SMBus (Four Levels) Selectable Pre-Emphasis and Equalization Eliminate ISI Jitter
  • Wide Input Common Mode Range Enables Easy Interface to CML and LVPECL Drivers
  • LOS Circuitry Detects Open Inputs Fault Condition
  • On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, Minimizes Board Space The DS25CP114 Eliminates the On-Chip Input Termination for Added Design Flexibility.
  • 8 kV ESD on LVDS I/O Pins Protects Adjoining Components
  • Small 6 mm x 6 mm WQFN-40 Space Saving Package

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Technical documentation

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODELS Download
SNLM065.ZIP (20 KB) - IBIS Model
SIMULATION TOOLS Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
WQFN (RTA) 40 View options

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