Product details


Operating temperature range (C) -40 to 85 open-in-new Find other Other interfaces

Package | Pins | Size

WQFN (RHS) 48 49 mm² 7 x 7 open-in-new Find other Other interfaces


  • 5-bit DDR LVDS Parallel Data Interface
  • Programmable Transmit De-emphasis
  • Configurable Output Levels (VOD)
  • Selectable DC-balanced Encoder
  • Selectable Data Scrambler
  • Remote Sense for Automatic Detection and Negotiation of Link Status
  • On Chip LC VCOs
  • Redundant Serial Output (ELX device only)
  • Data Valid Signaling to Assist with Synchronization of Multiple Receivers
  • Supports AC- and DC-coupled Signaling
  • Integrated CML and LVDS Terminations
  • Configurable PLL Loop Bandwidth
  • Programmable Output Termination (50Ω or 75Ω).
  • Built-in Test Pattern Generator
  • Loss of Lock and Error Reporting
  • Configurable via SMBus
  • 48-pin WQFN Package with Exposed DAP

Key Specifications

  • 1.25 to 3.125 Gbps Serial Data Rate
  • 125 to 312.5 MHz DDR Parallel Clock
  • -40° to +85°C Temperature Range
  • >8 kV ESD (HBM) Protection
  • Low Intrinsic Jitter — 35ps at 3.125 Gbps

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The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.

The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.

The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.

The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet DS32EL0421/ELX0421 125 - 312.5 MHz FPGA-Link Serializer w/ DDR LVDS Parallel I/F datasheet (Rev. F) Apr. 15, 2013
Application note Expanding the Payload w/FPGA-Link DS32ELX0421 and DS32ELX0124 SER/DES (Rev. A) Apr. 26, 2013
Application note LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers (Rev. A) Apr. 26, 2013

Design & development

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Design tools & simulation

SNLM198.ZIP (52 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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WQFN (RHS) 48 View options

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