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DS32ELX0124

ACTIVE

125 to 312.5-MHz FPGA-link deserializer with DDR LVDS parallel interface

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Data sheet

DS32ELX0124

ACTIVE
Data sheet Order now

Product details

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (RHS) 48 49 mm² (7 mm × 7 mm)
  • 5-bit DDR LVDS Parallel Data Interface
  • Programmable Receive Equalization
  • Selectable DC-Balance Decoder
  • Selectable De-Scrambler
  • Remote Sense for Automatic Detection and Negotiation of Link Status
  • No External Receiver Reference Clock Required
  • LVDS Parallel Interface
  • Programmable LVDS Output Clock Delay
  • Supports Output Data-Valid Signaling
  • Supports Keep-Alive Clock Output
  • On Chip LC VCOs
  • Redundant Serial Input (ELX device only)
  • Retimed Serial Output (ELX device only)
  • Configurable PLL Loop Bandwidth
  • Configurable via SMBus
  • Loss of Lock and Error Reporting
  • 48-pin WQFN Package with Exposed DAP

Key Specifications

  • 1.25 to 3.125 Gbps Serial Data Rate
  • 125 to 312.5 MHz DDR Parallel Clock
  • -40° to +85°C Temperature Range
  • > 8 kV ESD (HBM) Protection
  • 0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)

All trademarks are the property of their respective owners.

  • 5-bit DDR LVDS Parallel Data Interface
  • Programmable Receive Equalization
  • Selectable DC-Balance Decoder
  • Selectable De-Scrambler
  • Remote Sense for Automatic Detection and Negotiation of Link Status
  • No External Receiver Reference Clock Required
  • LVDS Parallel Interface
  • Programmable LVDS Output Clock Delay
  • Supports Output Data-Valid Signaling
  • Supports Keep-Alive Clock Output
  • On Chip LC VCOs
  • Redundant Serial Input (ELX device only)
  • Retimed Serial Output (ELX device only)
  • Configurable PLL Loop Bandwidth
  • Configurable via SMBus
  • Loss of Lock and Error Reporting
  • 48-pin WQFN Package with Exposed DAP

Key Specifications

  • 1.25 to 3.125 Gbps Serial Data Rate
  • 125 to 312.5 MHz DDR Parallel Clock
  • -40° to +85°C Temperature Range
  • > 8 kV ESD (HBM) Protection
  • 0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)

All trademarks are the property of their respective owners.

The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.

The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.

The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.

The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.

The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.

The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.

The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.

The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet DS32EL0124/ELX0124 125MHz-312.5MHz FPGA-Link Deserializr w/DDR LVDS Para I/F datasheet (Rev. K) Apr 15, 2013
Application note Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls Oct 29, 2020
Application note How to Design LVDS SerDes in Industrial Systems Jul 16, 2018
Application note LVDS Timing DS32ELX0421 and DS32ELX0124 Serializers and Deserializers (Rev. A) Apr 26, 2013
Application note Expanding the Payload w/FPGA-Link DS32ELX0421 and DS32ELX0124 SER/DES (Rev. A) Apr 26, 2013

Design & development

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Simulation model

DS32ELX0124 IBIS Model

SNLM199.ZIP (56 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
WQFN (RHS) 48 Ultra Librarian
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