Home Interface High-speed SerDes FPD-Link SerDes
Home
Interface
High-speed SerDes
FPD-Link SerDes

DS90CF363B

ACTIVE

+3.3V Falling Edge LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link - 65MHz

Order now
Data sheet

DS90CF363B

ACTIVE
Data sheet Order now

Product details

Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link LVDS Color depth (bpp) 18 Features Low-EMI Point-to-Point Communication Rating Catalog Operating temperature range (°C) -10 to 70
Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link LVDS Color depth (bpp) 18 Features Low-EMI Point-to-Point Communication Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered.
  • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5% Down Spread.
  • "Input Clock Detection" Feature will Pull all LVDS Pairs to Logic Low when Input Clock is Missing and when /PD Pin is Logic High.
  • 18 to 68 MHz Shift Clock Support
  • Best–in–Class Set & Hold Times on TxINPUTs
  • Tx Power Consumption < 130 mW (typ) @65MHz Grayscale
  • 40% Less Power Dissipation than BiCMOS Alternatives
  • Tx Power-Down Mode < 37μW (typ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 1.3 Gbps Throughput
  • Up to 170 Megabytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires no External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 48-lead TSSOP Package
  • Improved Replacement for:
    • SN75LVDS84, DS90CF363A

All trademarks are the property of their respective owners.

  • No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered.
  • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5% Down Spread.
  • "Input Clock Detection" Feature will Pull all LVDS Pairs to Logic Low when Input Clock is Missing and when /PD Pin is Logic High.
  • 18 to 68 MHz Shift Clock Support
  • Best–in–Class Set & Hold Times on TxINPUTs
  • Tx Power Consumption < 130 mW (typ) @65MHz Grayscale
  • 40% Less Power Dissipation than BiCMOS Alternatives
  • Tx Power-Down Mode < 37μW (typ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 1.3 Gbps Throughput
  • Up to 170 Megabytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires no External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 48-lead TSSOP Package
  • Improved Replacement for:
    • SN75LVDS84, DS90CF363A

All trademarks are the property of their respective owners.

The DS90CF363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90CF363B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF366) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90CF363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90CF363B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF366) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
filter Find other FPD-Link SerDes
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 8
Top documentation Type Title Format options Date
* Data sheet DS90CF363B 3.3V Prog LVDS Transm 18-Bit FPDLink -65 MHz datasheet (Rev. D) 17 Apr 2013
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 Nov 2018
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29 Jun 2018
Application note AN-1032 An Introduction to FPD-Link (Rev. C) 08 Aug 2017
Application note Receiver Skew Margin for Channel Link I and FPD Link I Devices 13 Jan 2016
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15 May 2004
Application note AN-1056 STN Application Using FPD-Link 14 May 2004
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14 May 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

FLINK3V8BT-85 — Evaluation kit for FPD-Link family of serializer and deserializer LVDS devices

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

User guide: PDF
Not available on TI.com
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
View Options
Package Pins CAD symbols, footprints & 3D models
TSSOP (DGG) 48 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos