5-43MHz DC-Balanced 24-Bit FPD-Link II Serializer - Automotive Grade



Product details


Function Serializer Color depth (bpp) 18 Input compatibility LVCMOS Pixel clock frequency (Max) (MHz) 43 Output compatibility FPD-Link LVDS Features Capable to Drive up to 10 meters STP Cable, Hot Plug Support Signal conditioning Pre-emphasis, VOD Select EMI reduction LVDS, Slew Rate Control, Progressive Turn On (PTO), BIST Diagnostics BIST Operating temperature range (C) -40 to 105 open-in-new Find other FPD-Link SerDes

Package | Pins | Size

TQFP (PFB) 48 81 mm² 9 x 9 open-in-new Find other FPD-Link SerDes


  • Supports Displays With 18-Bit Color Depth
  • 5-MHz to 43-MHz Pixel Clock
  • Automotive-Grade Product AEC-Q100 Grade 2
  • 24:1 Interface Compression
  • Embedded Clock With DC Balancing Supports
    AC-Coupled Data Transmission
  • Capable to Drive up to 10 Meters Shielded
    Twisted-Pair Cable
  • No Reference Clock Required (Deserializer)
  • Meets ISO 10605 ESD – Greater than 8 kV HBM
    ESD Structure
  • Hot Plug Support
  • EMI Reduction – Serializer Accepts Spread
    Spectrum Input; Data Randomization and
    Shuffling on Serial Link; Deserializer Provides
    Adjustable PTO (Progressive Turnon) LVCMOS
  • @Speed BIST (Built-In Self-Test) to Validate
    LVDS Transmission Path
  • Individual Power-Down Controls for Both
    Transmitter and Receiver
  • Power Supply Range 3.3 V ±10%
  • 48-Pin TQFP Package for Transmitter and 64-Pin
    TQFP Package for Receiver
  • Temperature Range: –40°C to 105°C
  • Backward-Compatible Mode With
open-in-new Find other FPD-Link SerDes


The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.

open-in-new Find other FPD-Link SerDes

Technical documentation

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The SERDESUR-43 is an evaluation kit designed to demonstrate performance and capabilities of the DS90UR124 and DS90UR241 FPD-Link II Serializer/Deserializer Chipset.

The DS90UR241 Serializer board accepts LVCMOS input signals and provides single serialized FPD-LInk II LVDS data pair as an output. The (...)

Design tools & simulation

SNLM026.ZIP (7 KB) - IBIS Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide
SNLC003.ZIP (125 KB)

Reference designs

WVGA Digital Video SerDes for Automotive TFT LCD Displays w/ DVP Interface
TIDA-00137 The TIDA-00137 reference design is a high speed serial video interface to connect a remote automotive WVGA TFT LCD display with DVP (LVCMOS) Interface to a video processing system. It uses TIs FPD-Link II SerDes technology to transmit uncompressed video data over shielded twisted pair cable (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
TQFP (PFB) 48 View options

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