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The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra low power dissipation, low noise, and high data rates. The BLVDS side is a transceiver with a separate channel acting as a return/source clock.
The DS92CK16 accepts LVDS (300 mV typical) differential input levels, and translates them to 3V CMOS output levels. An output enable pin OE , when high, forces all CLKOUT pins high.
The device can be used as a source synchronous driver. The selection of the source driving is controlled by the CrdCLKIN and DE pins. This device can be the master clock, driving the inputs of other clock I/O pins in a multipoint environment. Easy master/slave clock selection is achieved along a backplane.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver datasheet (Rev. C) | Apr 13, 2013 | |
| Application note | High Speed BUS LVDS Clock Distri Using DS92CK16 Clock Distri (Rev. B) | Apr 26, 2013 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| TSSOP (PW) | 24 | Ultra Librarian |
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