Product details


Function Serializer Signal conditioning De-Emphasis EMI reduction SSC Compatible, VOD Control, LVDS Inputs Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Display SerDes


  • 5-Channel (4 data + 1 clock) Channel Link LVDS Parallel Interface Supports 24-bit Data
    3-bit Control at 5 – 50 MHz
  • AC Coupled STP Interconnect up to 10 Meters in Length
  • Integrated Serial CML Terminations
  • AT–SPEED BIST Mode and Status Pin
  • Optional I2C Compatible Serial Control Bus
  • Power Down Mode Minimizes Power Dissipation
  • 1.8V or 3.3V Compatible Control Pin Interface
  • >8 kV ESD (HBM) Protection
  • -40° to +85°C Temperature Range

  • Data Scrambler for Reduced EMI
  • DC–Balance Encoder for AC Coupling
  • Selectable Output VOD and Adjustable De-Emphasis

  • Random Data Lock; No Reference Clock Required
  • Adjustable Input Receiver Equalization
  • EMI Minimization on Output Parallel Bus (Spread Spectrum Clock Generation and LVDS VOD Select)

All trademarks are the property of their respective owners.

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The DS92LV0411 (serializer) and DS92LV0412 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair.

The DS92LV0411/DS92LV0412 enables applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock interface to reduce interconnect cost or ease design challenges. The parallel LVDS interface also reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer distance transmission over lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” operation.

The DS92LV0411 and DS92LV0412 are programmable though an I2C interface as well as by pins. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

The DS92LV0411 and DS92LV0412 can be used interchangeably with the DS92LV2411 or DS92LV2412. This allows designers the flexibility to connect to the host device and receiving devices with different interface types, LVDS or LVCMOS.

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Technical documentation

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Type Title Date
* Datasheet DS92LV0411/12 5 - 50MHz Ch Link II SER/DES with LVDS Parallel Interface datasheet (Rev. B) Apr. 16, 2013
Application notes High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs Nov. 09, 2018
Selection guides Channel Link SerDes Nov. 06, 2013
Application notes DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) Apr. 29, 2013
User guides LV04EVK01 Channel Link to Channel Link II Converter Evaluation Kit Feb. 01, 2012
User guides Channel Link II Design Guide Jan. 21, 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The LV04EVK01 is an evaluation kit designed to demonstrate performance and capabilities of the DS92LV0421 and DS92LV0422 Channel Link II Serializer/Deserializer chipset.

The DS92LV0421 serializer board accepts LVDS input signals and provides a single serialized Channel Link II CML data pair as an (...)



  • One serializer board with the DS92LV0421
  • One deserializer board with the DS92LV0422
  • One 2-meter USB 2.0 Hi-SPEED cable assembly
  • Evaluation kit documentation

What the user needs to provide

  • A 24-bit data bus and clock source with LVDS outputs - for example a video generator
  • A data error checker or (...)

Design tools & simulation

SNLM128.ZIP (59 KB) - IBIS Model
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
(NJK) 36 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​


High-speed layout guidelines for reducing EMI in LVDS SerDes designs

This video provides guidelines on how to reduce EMI in designs that use TI serializers and deserializers.

Posted: 13-Jan-2018
Duration: 08:16

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