DS99R124AQ-Q1 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter | TI.com

DS99R124AQ-Q1 (ACTIVE) 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter



The DS99R124AQ converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects.

The DS99R124AQ converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided.

Adjustable input equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces the medium-induced deterministic jitter. EMI is minimized by the use of low voltage differential signaling, output state select feature, and additional output spread spectrum generation.

With fewer wires to the physical interface of the display, FPD-Link output with LVDS technology is ideal for high speed, low power and low EMI data transfer.

The DS99R124AQ is offered in a 48-pin WQFN package and is specified over the automotive AEC-Q100 Grade 2 temperature range of -40˚C to +105˚C.


  • 5 – 43 MHz Support (140 Mbps to 1.2 Gbps Serial Link)
  • 4-Channel (3 data + 1 clock) FPD-Link LVDS Outputs
  • 3 Low-Speed Over-Sampled LVCMOS Outputs
  • AC Coupled STP Interconnect up to 10 Meters in Length
  • Integrated Input Termination
  • @ Speed Link BIST Mode and Reporting Pin
  • Optional I2C Compatible Serial Control Bus
  • RGB666 + VS, HS, DE Converted from 1 Pair
  • Power Down Mode Minimizes Power Dissipation
  • FAST Random Data Lock; No Reference Clock Required
  • Adjustable Input Receive Equalization
  • LOCK (Real Time Link Status) Reporting Pin
  • Low EMI FPD-Link Output
  • SSCG Option for Lower EMI
  • 1.8V or 3.3V Compatible I/O Interface
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • >8 kV HBM and ISO 10605 ESD Rating

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Part number Order Function Color depth (bpp) Pixel clock min (MHz) Pixel clock (Max) (MHz) Input compatibility Output compatibility Features Signal conditioning EMI reduction Diagnostics Total throughput (Mbps) Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG)
DS99R124AQ-Q1 Order now Deserializer     18     5     43     FPD-Link II LVDS     FPD-Link LVDS     I2C Config     Equalizer     SSCG
LVDS Outputs    
BIST     1032     Automotive     -40 to 105     WQFN | 48     48WQFN: 49 mm2: 7 x 7 (WQFN | 48)