HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface
Product details
Parameters
Package | Pins | Size
Features
- 5-Bit LVDS Interface
- No External VCO or Clock Required
- Reclocked Serial Loopthrough With Cable Driver
- Powerdown Mode
- 3.3V SMBus Configuration Interface
- Small 48-Pin WQFN Package
- Industrial Temperature range: -40°C to +85°C
Key Specifications
- Output compliant with SMPTE 259M-C, SMPTE 292M, SMPTE 424M and DVB-ASI
- Typical power dissipation: 590 mW (loopthrough disabled, 3G datarate)
- 0.6 UI Minimum Input Jitter Tolerance
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Description
The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.
The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.
The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | LMH0341/041/071/051 3Gbps, HD, SD, DVB-ASI SDI Deserializr w/Loopthru & LVDS I/F datasheet (Rev. Q) | Apr. 16, 2013 |
Selection guide | Broadcast and Professional Video Interface Solutions (Rev. E) | Apr. 05, 2017 | |
Application note | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | Apr. 26, 2013 | |
Application note | AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A) | Apr. 26, 2013 | |
Application note | AN-2145 Power Considerations for SDI Products (Rev. B) | Apr. 26, 2013 | |
Application note | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | Apr. 26, 2013 | |
Application note | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | Nov. 12, 2009 | |
Application note | A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video | Mar. 18, 2008 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Software development
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
WQFN (RHS) | 48 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
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