The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS.
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|Part number||Order||DDR memory type||Control mode||Iout VTT (Max) (A)||Iq (Typ) (mA)||Output||Vin (Min) (V)||Vin (Max) (V)||Features||Rating||Operating temperature range (C)||Package Group||Package size: mm2:W x L (PKG)|
|2.2||5.5||Catalog||0 to 125||
SO PowerPAD | 8
SOIC | 8
WQFN | 16
8SO PowerPAD: 19 mm2: 3.9 x 4.89 (SO PowerPAD | 8)
8SOIC: 19 mm2: 3.91 x 4.9 (SOIC | 8)
16WQFN: 16 mm2: 4 x 4 (WQFN | 16)