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Product details

Parameters

DDR memory type DDR Control mode Iout VTT (Max) (A) 1.5 Iq (Typ) (mA) 0.25 Output VREF, VTT Vin (Min) (V) 2.2 Vin (Max) (V) 5.5 Features Rating Catalog Operating temperature range (C) 0 to 125 open-in-new Find other DDR memory power ICs

Package | Pins | Size

HSOIC (DDA) 8 19 mm² 4.9 x 3.9 SOIC (D) 8 19 mm² 4.9 x 3.9 WQFN (NHP) 16 16 mm² 4 x 4 open-in-new Find other DDR memory power ICs

Features

  • Low Output Voltage Offset
  • Works with +5v, +3.3v and 2.5v Rails
  • Source and Sink Current
  • Low External Component Count
  • No External Resistors Required
  • Linear Topology
  • Available in SOIC-8, SO PowerPAD-8 or WQFN-16 Packages
  • Low Cost and Easy to Use

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Description

The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2995 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DDR DIMMS.

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Technical documentation

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Type Title Date
* Data sheet LP2995 DDR Termination Regulator datasheet (Rev. M) Mar. 19, 2013
Application note Limiting DDR Termination Regulators’ Inrush Current Aug. 23, 2016
User guide AN-1241 LP2995 Evaluation Board (Rev. B) May 07, 2013
Application note AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) May 06, 2013
Application note DDR-SDRAM Termination Simplified Using A Linear Regulator Jul. 23, 2002

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODEL Download
SNVMAH5.ZIP (4 KB) - PSpice Model
SIMULATION MODEL Download
SNVMAH6.ZIP (71 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
High efficiency power supply architecture reference design for protection relay processor module
TIDA-010011 — This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SO PowerPAD (DDA) 8 View options
SOIC (D) 8 View options
WQFN (NHP) 16 View options

Ordering & quality

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  • MSL rating/Peak reflow
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  • Qualification summary
  • Ongoing reliability monitoring

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