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Product details

Parameters

DDR memory type DDR2 Control mode Iout VTT (Max) (A) 0.5 Iq (Typ) (mA) 0.32 Output VREF, VTT Vin (Min) (V) 1.8 Vin (Max) (V) 5.5 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (C) 0 to 125 open-in-new Find other DDR memory power ICs

Package | Pins | Size

HSOIC (DDA) 8 19 mm² 4.9 x 3.9 SOIC (D) 8 19 mm² 4.9 x 3.9 open-in-new Find other DDR memory power ICs

Features

  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
  • Available in SOIC-8, SO PowerPAD-8 Packages

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Description

The LP2997 linear regulator is designed to meet the JEDEC SSTL-18 specifications for termination of DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 500mA continuous current and transient peaks up to 900mA in the application as required for DDR-II SDRAM termination. The LP2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2997 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

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LP2996-N ACTIVE 1.5A DDR termination regulator with shutdown pin for DDR2 DDR-I And DDR-II Linear Termination Regulator

Technical documentation

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Type Title Date
* Data sheet LP2997 DDR-II Termination Regulator datasheet (Rev. F) Apr. 04, 2013
Application note Limiting DDR Termination Regulators’ Inrush Current Aug. 23, 2016
Application note AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) May 06, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODEL Download
SNVMAH7.ZIP (70 KB) - PSpice Model
SIMULATION MODEL Download
SNVMAH8.ZIP (4 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
High efficiency power supply architecture reference design for protection relay processor module
TIDA-010011 — This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SO PowerPAD (DDA) 8 View options
SOIC (D) 8 View options

Ordering & quality

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