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LP2998

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1.5-A DDR termination regulator with shutdown pin

Data sheet
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1.5-A DDR termination regulator with shutdown pin

LP2998

ACTIVE
Data sheet Order now

Product details

Parameters

DDR memory type DDR, DDR2, DDR3, DDR3L Control mode — Iout VTT (Max) (A) 1.5 Iq (Typ) (mA) 0.32 Output VREF, VTT Vin (Min) (V) 1.35 Vin (Max) (V) 5.5 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (C) -40 to 125 open-in-new Find other DDR memory power ICs

Package | Pins | Size

HSOIC (DDA) 8 19 mm² 4.9 x 3.9 SOIC (D) 8 19 mm² 4.9 x 3.9 open-in-new Find other DDR memory power ICs

Features

  • AEC-Q100 Test Guidance with the following results
    (SO PowerPAD-8):
    • Device HBM ESD Classification Level H1C
    • Junction Temperature Range –40°C to 125°C
  • 1.35 V Minimum VDDQ
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Low External Component Count
  • Thermal Shutdown
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Description

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

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Technical documentation

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Type Title Date
* Data sheet LP2998/LP2998-Q1 DDR Termination Regulator datasheet (Rev. K) Aug. 20, 2014
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) Jul. 09, 2020
Selection guide TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
Application note Limiting DDR Termination Regulators’ Inrush Current Aug. 23, 2016
User guide AN-1813 LP2998 Evaluation Board (Rev. A) May 07, 2013
Application note AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) May 06, 2013
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs Apr. 28, 2010
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices Apr. 20, 2010
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) Mar. 31, 2010
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) Mar. 26, 2010
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs Mar. 26, 2010
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers Mar. 26, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description

The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.

View details

Design tools & simulation

SIMULATION MODEL Download
SNVM695B.ZIP (48 KB) - PSpice Model
SIMULATION MODEL Download
SNVMAF5.ZIP (7 KB) - PSpice Model
SIMULATION MODEL Download
SNVMB48.ZIP (39 KB) - TINA-TI Spice Model
SIMULATION MODEL Download
SNVMB49.TSC (599 KB) - TINA-TI Reference Design

Reference designs

REFERENCE DESIGNS Download
High efficiency power supply architecture reference design for protection relay processor module
TIDA-010011 — This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
document-generic Schematic
REFERENCE DESIGNS Download
Xilinx® Zynq® 7000 series (XC7Z015) Power Solution, 8W - Reference Design
PMP10601 — The PMP10601 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015)  FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It also (...)
document-generic Schematic
REFERENCE DESIGNS Download
Xilinx Kintex UltraScale XCKU040 FPGA Power Solution, 6W Reference Design
PMP10630 — The PMP10630 reference design is a complete high density power solution for Xilinx® Kintex® UltraScale™ XCKU040 FPGA. This design uses an optimal combination of SIMPLE SWITCHER® modules and LDOs to provide all the necessary voltage rails in a small solution size of 36 x 43 mm (1.4 (...)
document-generic Schematic
REFERENCE DESIGNS Download
Xilinx® Zynq®7000 series (XC7Z015) Power Solution, 5W - Reference Design
PMP10600 — The PMP10600.1 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator.  It also features one LM3880 for power up and power down (...)
document-generic Schematic
REFERENCE DESIGNS Download
Xilinx Zynq 7000 Series (XC7Z045) 20W Reference Design
PMP10613 — The PMP10613 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z045)  FPGA.   This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator to provide all the necessary rails to power the FPGA.  It (...)
document-generic Schematic
REFERENCE DESIGNS Download
Supercapacitor Backup Power Supply with Active Cell Balancing Reference Design
PMP9766 — This reference design describes a backup power circuit which addresses instantaneous protection against power interruptions by using a buck-boost converter and two stacked supercapacitors. The implementation is based on a completely integrated TPS63020 buck-boost converter circuit enabling a small (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SO PowerPAD (DDA) 8 View options
SOIC (D) 8 View options

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