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Product details

Parameters

DSP 1 C674x Operating system Linux, SYS/BIOS On-chip L2 cache/RAM 256 KB (DSP) Other on-chip memory 128 KB Total on-chip memory (KB) 448 DRAM DDR2, LPDDR Ethernet MAC 10/100 Serial I/O I2C, McASP, McBSP, SPI, UART SPI 2 I2C 2 USB 1 Arm MHz (Max.) 200 Arm CPU 1 Arm9 UART (SCI) 3 Operating temperature range (C) -40 to 105, 0 to 90 Rating Catalog open-in-new Find other C6000 DSP + Arm processors

Package | Pins | Size

NFBGA (ZWT) 361 256 mm² 16 x 16 open-in-new Find other C6000 DSP + Arm processors

Features

  • Dual-Core SoC
    • 200-MHz ARM926EJ-S RISC MPU
    • 200-MHz C674x Fixed- and Floating-Point VLIW DSP
  • ARM926EJ-S Core
    • 32- and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single-Cycle MAC
    • ARM Jazelle Technology
    • Embedded ICE-RT for Real-Time Debug
  • ARM9 Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 1600 MIPS and 1200 MFLOPS
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Channel Controllers
    • 3 Transfer Controllers
    • 64 Independent DMA Channels
    • 16 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Floating-Point VLIW DSP Core
    • Load-Store Architecture With Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units:
      • Mixed-Precision IEEE Floating-Point Multiply Supported up to:
        • 2 SP × SP → SP Per Clock
        • 2 SP × SP → DP Every Two Clocks
        • 2 SP × DP → DP Every Three Clocks
        • 2 DP × DP → DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 × 32-Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • Software Support
    • TI DSPBIOS
    • Chip Support Library and DSP Library
  • 128KB of RAM Shared Memory
  • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM With 128-MB Address Space
    • DDR2/Mobile DDR Memory Controller With one of the Following:
      • 16-Bit DDR2 SDRAM With 256-MB Address Space
      • 16-Bit mDDR SDRAM With 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • With Modem Control Signals
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects
  • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces
  • Two Master and Slave Inter-Integrated Circuits
    (I2C Bus™)
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Real-Time Unit (PRU) Cores
      • 32-Bit Load-Store RISC Architecture
      • 4KB of Instruction RAM Per Core
      • 512 Bytes of Data RAM Per Core
      • PRUSS can be Disabled Through Software to Save Power
      • Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R31 Output of the PRU Cores.
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 2.0 OTG Port With Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
  • One Multichannel Audio Serial Port (McASP):
    • Two Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable
    • FIFO Buffers for Transmit and Receive
  • Two Multichannel Buffered Serial Ports (McBSPs):
    • Supports TDM, I2S, and Similar Formats
    • AC97 Audio Codec Interface
    • Telecom Interfaces (ST-Bus, H100)
    • 128-Channel TDM
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant
    • MII Media-Independent Interface
    • RMII Reduced Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock (RTC) With 32-kHz Oscillator and Separate Power Rail
  • Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Two Enhanced High-Resolution Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter With Period and Frequency Control
    • 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Timestamps
  • Packages:
    • 361-Ball Pb-Free PBGA [ZWT Suffix],
      0.80-mm Ball Pitch
  • Commercial or Extended Temperature

All trademarks are the property of their respective owners.

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Description

The OMAP-L132 C6000 DSP+ARM processor is a low-power applications processor based on an ARM926EJ-S and a C674x DSP core. This processor provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution.

The dual-core architecture of the device provides benefits of both DSP and reduced instruction set computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM9 core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM9 core has separate 16-KB instruction and 16-KB data caches. Both caches are 4-way associative with virtual index virtual tag (VIVT). The ARM9 core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The device DSP core uses a 2-level cache-based architecture. The level 1 program cache (L1P) is a
32-KB direct mapped cache, and the level 1 data cache (L1D) is a 32-KB 2-way, set-associative cache. The level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by the ARM9 and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

For security-enabled devices, TI’s Basic Secure Boot lets users protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust," the secure boot flow ensures a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks; however, the JTAG port can be enabled during the secure boot process during application development. The boot modules are encrypted while sitting in external nonvolatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. Encryption and decryption protects customers’ IP and lets them securely set up the system and begin device operation with known, trusted code.

Basic Secure Boot uses either SHA-1 or SHA-256, and AES-128 for boot image validation. Basic Secure Boot also uses AES-128 for boot image encryption. The secure boot flow employs a multilayer encryption scheme which not only protects the boot process but also offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect customer encryption keys. When an update is needed, the customer creates a new encrypted image. Then the device can acquire the image through an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, see the .

The peripheral set includes: a 10/100 Mbps Ethernet media access controller (EMAC) with a management data input/output (MDIO) module; one USB2.0 OTG interface; two I2C Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as a watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 APWM outputs; two external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

The EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM9 and DSP. These tools include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet OMAP-L132 C6000™ DSP+ARM Processor datasheet (Rev. E) Jan. 31, 2017
* Errata OMAP-L132 C6000 DSP+ARM Processor Errata (Silicon Revisions 2.3, 2.1) (Rev. G) Mar. 21, 2014
* User guides OMAP-L132 C6000 DSP+ARM Processor Technical Reference Manual (Rev. C) Sep. 12, 2016
User guides SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) Jun. 01, 2020
User guides ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Y) Feb. 04, 2020
User guides ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. V) Feb. 04, 2020
Application notes Programming mDDR/DDR2 EMIF on OMAP-L1x/C674x Dec. 20, 2019
User guides L138/C6748 development kit (LCDK) (Rev. A) Sep. 18, 2019
Application notes OMAPL138/C6748 ROM Bootloader Resources and FAQ Jun. 24, 2019
Application notes Using DSPLIB FFT Implementation for Real Input and Without Data Scaling Jun. 11, 2019
Application notes TDA2x/TDA2E Performance (Rev. A) Jun. 10, 2019
User guides ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) Jun. 03, 2019
User guides ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) Jun. 03, 2019
Application notes OMAP-L132/L138 Power Consumption Summary Apr. 01, 2019
Application notes General Hardware Design/BGA PCB Design/BGA Feb. 22, 2019
Application notes OMAP-L13x / C674x / AM1x schematic review guidelines Feb. 14, 2019
Application notes Using the OMAP-L132/L138 Bootloader Application Report (Rev. F) Jan. 22, 2019
Application notes McASP Design Guide - Tips, Tricks, and Practical Examples Jan. 10, 2019
User guides ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) Nov. 19, 2018
User guides ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) Nov. 19, 2018
User guides PRU Assembly Instruction User Guide Feb. 16, 2018
User guides SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. U) Feb. 07, 2018
User guides ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) Jan. 16, 2018
User guides ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) Jan. 16, 2018
User guides ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) Sep. 30, 2017
User guides ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) Sep. 30, 2017
User guides ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) Jun. 21, 2017
User guides ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) Jun. 21, 2017
Application notes Processor SDK RTOS Audio Benchmark Starter Kit Apr. 12, 2017
User guides ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) Apr. 30, 2016
User guides ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) Apr. 30, 2016
Application notes TI DSP Benchmarking Jan. 13, 2016
User guides ARM Assembly Language Tools v5.2 User's Guide (Rev. M) Nov. 05, 2014
User guides ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) Nov. 05, 2014
Application notes OMAP-L132/L138, TMS320C6742/6/8 Pin Multiplexing Utility (Rev. B) Sep. 27, 2013
User guides TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) Aug. 21, 2012
User guides TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) Aug. 21, 2012
Application notes Powering the OMAP-L132/OMAP-L137/OMAP-L138 Processor with the TPS650061 Apr. 13, 2012
White papers MityDSP®-L138F Software Defined Radio Using uPP Data Transfer (Rev. A) Feb. 02, 2012
Application notes Powering the TMS320C6742, TMS320C6746, and TMS320C6748 With the TPS650061 Dec. 19, 2011
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guides TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F) Sep. 14, 2011
Application notes High-Vin, High-Efficiency Power Solution Using DC/DC Converter With DVFS (Rev. C) Aug. 29, 2011
Application notes Powering OMAP-L132/L138, C6742/4/6, and AM18x with TPS65070 (Rev. B) Aug. 29, 2011
Application notes Simple Power Solution Using LDOs (Rev. B) Aug. 29, 2011
White papers OpenCV on TI’s DSP+ARM® Jul. 27, 2011
Application notes TMS320C674x/OMAP-L1x Processor Security Jun. 08, 2011
More literature OMAP-L1x C6000 DSP+ARM Processors Product Bulletin (Rev. A) Mar. 10, 2011
User guides TMS320C674x DSP Megamodule Reference Guide (Rev. A) Aug. 03, 2010
User guides TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B) Jul. 30, 2010
Application notes High-Efficiency Power Solution Using DC/DC Converters With DVFS (Rev. A) May 05, 2010
Application notes High-Integration, High-Efficiency Power Solution Using DC/DC Converters w/DVFS (Rev. A) May 05, 2010
Application notes Canny Edge Detection Implementation on TMS320C64x/64x+ Using VLIB Nov. 25, 2009
Application notes TMS320C6748/46/42 & OMAP-L132/L138 USB Downstream Host Compliance Testing Aug. 17, 2009
Application notes TMS320C6748/46/42 & OMAP-L1x8 USB Upstream Device Compliance Testing Aug. 17, 2009
White papers Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core Jun. 24, 2009
Application notes TMS320C674x/OMAP-L1x USB Compliance Checklist Mar. 12, 2009
User guides TMS320C674x DSP Cache User's Guide (Rev. A) Feb. 11, 2009
Application notes Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) Jul. 17, 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

DEVELOPMENT KITS Download
document-generic User guide
195
Description

The OMAP-L138 DSP+ARM9™ development kit will enable fast and easy Linux software and hardware development. This scalable platform will ease and accelerate software and hardware development of everyday applications that require real-time signal processing and control functional, including (...)

Features
  • Integrated floating-/fixed-point DSP with up to 456 MHz performance; and ARM9 with up to 456 MHz performance
  • Software, expansion headers, schematics and application demos
  • SDKs, DSP/BIOS RTOS, drivers, stacks and protocol, algorithm libraries, flash and boot utilities and StarterWare
DEVELOPMENT KITS Download
document-generic User guide
195
Description

The TMS320C6748 DSP development kit (LCDK) is a scalable platform that breaks down development barriers for applications that require embedded analytics and real-time signal processing, including biometric analytics, communications and audio. The low-cost LCDK will also speed and ease your hardware (...)

Features
  • Integrated floating-/fixed-point DSP with up to 456 MHz performance
  • Software, expansion headers, schematics and application demos
  • SDKs, DSP/BIOS RTOS, drivers, stacks and protocol, algorithm libraries, flash and boot utilities and StarterWare

Software development

SOFTWARE DEVELOPMENT KITS (SDK) Download
Processor SDK for OMAPL138 Processors for Linux and TI-RTOS Support
PROCESSOR-SDK-OMAPL138 Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
Features

Linux Features:

  • Open Linux support
  • Linux kernel and Bootloaders
  • File system
  • Example applications, including:
    • ARM benchmarks Dhrystone, Linpack, Whetstone
  • Code Composer Studio™ IDE for Linux development
  • Documentation

RTOS Features:

  • Full driver availability
  • Debug and instrumentation utilities
  • Board support (...)
SOFTWARE DEVELOPMENT KITS (SDK) Download
Windows® Embedded Compact/CE SDK - ARM9™-based AM18x, OMAP-L13x Processor
WINCESDK-AM1XOMAPL1X Microsoft Windows Embedded Compact (WEC7) and CE (WinCE 6.0) operating systems are optimized for embedded devices that require minimum storage based on a componentized architecture.

WinCE BSPs for ARM9-based processors are now available from Adeneo Embedded.

DEBUG PROBES Download
XDS200 USB Debug Probe
TMDSEMU200-U The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)
295
Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

995
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

1495
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DRIVERS & LIBRARIES Download
DSP Math Library for Floating Point Devices
MATHLIB — The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
Features
  • Types of functions included:
    • Trigonometric and hyperbolic: Sin, Cos, Tan, Arctan, etc.
    • Power, exponential, and logarithmic
    • Reciprocal
    • Square root
    • Division
  • Natural C Source Code
  • Optimized C code with Intrinsics
  • Hand-coded assembly-optimized routines
  • C-callable routines, which can be inlined and are fully (...)
DRIVERS & LIBRARIES Download
TMS320C5000/6000 Image Library (IMGLIB)
SPRC264 C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Image Analysis

  • Image boundry and perimeter
  • Morphological operation
  • Edge detection
  • Image Histogram
  • Image thresholding

Image filtering and format conversion

  • Color space conversion
  • Image convolution
  • Image correlation
  • Error diffusion
  • Median filtering
  • Pixel expansion

Image compression and decompression

  • Forward and (...)
DRIVERS & LIBRARIES Download
TMS320C6000 DSP Library (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
DRIVERS & LIBRARIES Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
IDES, CONFIGURATION, COMPILERS & DEBUGGERS Download
Code Composer Studio (CCS) Integrated Development Environment (IDE)
CCSTUDIO

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

OPERATING SYSTEMS (OS) Download
Mentor Graphics Nucleus RTOS
Provided by Mentor Graphics Corporation — Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify application (...)
SOFTWARE CODECS Download
Adaptive Digital Technologies DSP VOIP, speech and audio codecs
Provided by Adaptive Digital Technologies, Inc. — Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide solutions (...)
SOFTWARE CODECS Download
Vocal technologies DSP VoIP codecs
Provided by VOCAL Technologies, Ltd. — With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)

Design tools & simulation

SIMULATION MODELS Download
SPRM523A.ZIP (121 KB) - IBIS Model
CAD/CAE SYMBOLS Download
SPRM539.ZIP (7 KB)

Reference designs

REFERENCE DESIGNS Download
Powering the OMAP-L132/OMAP-L137/OMAP-L138 with the TPS650061
PR2084 — This reference design presents a complete power solution and low-cost, discrete sequencing circuit for the OMAP-L132, OMAP-L137, and OMAP-L138 processors.
Design files

CAD/CAE symbols

Package Pins Download
NFBGA (ZWT) 361 View options

Ordering & quality

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