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Product details

Parameters

DSP 1 C674x Operating system Linux, TI-RTOS On-chip L2 cache/RAM 256 KB (DSP) Other on-chip memory 128 KB Total on-chip memory (KB) 448 DRAM SDRAM Ethernet MAC 10/100 PCI/PCIe Serial I/O McASP, SPI, I2C, UART SPI 2 I2C 2 USB 2 Arm MHz (Max.) 456 Arm CPU 1 Arm9 Display type 1 Video port (configurable) 1 UART (SCI) 3 Operating temperature range (C) -40 to 105, -40 to 90, -40 to 125, 0 to 90 Rating Catalog open-in-new Find other C6000 DSP + Arm processors

Package | Pins | Size

BGA (ZKB) 256 289 mm² 17 x 17 open-in-new Find other C6000 DSP + Arm processors

Features

  • Software Support
    • TI DSP/BIOS
    • Chip Support Library and DSP Library
  • Dual Core SoC
    • 375- and 456-MHz ARM926EJ-S RISC MPU
    • 375- and 456-MHz C674x VLIW DSP
  • ARM926EJ-S Core
    • 32-Bit and 16-Bit (Thumb®) Instructions
    • DSP Instruction Extensions
    • Single Cycle MAC
    • ARM® Jazelle® Technology
    • Embedded ICE-RT™ for Real-Time Debug
  • ARM9™ Memory Architecture
    • 16KB of Instruction Cache
    • 16KB of Data Cache
    • 8KB of RAM (Vector Table)
    • 64KB of ROM
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2736 MFLOPS C674x
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Fixed- and Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP x SP -> SP Per Clock
        • 2 SP x SP -> DP Every Two Clocks
        • 2 SP x DP -> DP Every Three Clocks
        • 2 DP x DP -> DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop
      Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • 128KB of RAM Shared Memory
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Realtime Unit (PRU) Cores
      • 32-Bit Load and Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client
    • USB 2.0 High-, Full-, and Low-Speed Host
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock with 32-kHz Oscillator and Separate Power Rail
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • Commercial, Industrial, Extended, or Automotive Temperature
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Description

The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs.

The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program Memory Management Units (MMUs) with table look-aside buffers. The ARM core has separate 16-KB instruction and 16KB of data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The OMAP-L137 device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 56
Type Title Date
* Datasheet OMAP-L137 Low-Power Applications Processor datasheet (Rev. G) Jun. 17, 2014
* Errata OMAP-L137 C6000 DSP+ARM Processor Errata (Silicon Revs 3.0, 2.1, 2.0, 1.1 & 1.0) (Rev. I) Jun. 17, 2014
* User guide OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D) Sep. 21, 2016
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) Jun. 01, 2020
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Y) Feb. 04, 2020
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. V) Feb. 04, 2020
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) Jun. 03, 2019
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) Jun. 03, 2019
Application note General Hardware Design/BGA PCB Design/BGA Feb. 22, 2019
Application note OMAP-L13x / C674x / AM1x schematic review guidelines Feb. 14, 2019
Application note McASP Design Guide - Tips, Tricks, and Practical Examples Jan. 10, 2019
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) Nov. 19, 2018
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) Nov. 19, 2018
Application note High-Speed Interface Layout Guidelines (Rev. H) Oct. 11, 2018
White paper Designing professional audio mixers for every scenario Jun. 28, 2018
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) Jan. 16, 2018
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) Jan. 16, 2018
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) Sep. 30, 2017
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) Sep. 30, 2017
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) Jun. 21, 2017
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) Jun. 21, 2017
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) Apr. 30, 2016
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) Apr. 30, 2016
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) Nov. 05, 2014
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) Nov. 05, 2014
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) Aug. 21, 2012
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) Aug. 21, 2012
Application note Using the OMAP-L1x7 Bootloader (Rev. G) Jun. 01, 2012
Application note Powering the OMAP-L132/OMAP-L137/OMAP-L138 Processor with the TPS650061 Apr. 13, 2012
White paper MityDSP®-L138F Software Defined Radio Using uPP Data Transfer (Rev. A) Feb. 02, 2012
Application note Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guide TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F) Sep. 14, 2011
White paper OpenCV on TI’s DSP+ARM® Jul. 27, 2011
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market May 19, 2011
Application note Power Solution Using Discrete DC/DC Converters and LDOs (Rev. B) Aug. 26, 2010
User guide TMS320C674x DSP Megamodule Reference Guide (Rev. A) Aug. 03, 2010
User guide TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B) Jul. 30, 2010
Application note OMAP-L137 Power Consumption Summary Jun. 30, 2010
Application note Power Solution using LDO's (Rev. A) Mar. 25, 2010
Application note Power Solution using a Dual DCDC Converter and a LDO (Rev. A) Mar. 25, 2010
User guide TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) Mar. 18, 2010
User guide TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) Mar. 18, 2010
More literature OMAP-L1x Software Solutions Diagram (Rev. B) Dec. 07, 2009
Application note Canny Edge Detection Implementation on TMS320C64x/64x+ Using VLIB Nov. 25, 2009
Application note OMAP-L137 TMS320C6747/6745/6743 Pin Multiplexing Utility (Rev. A) Sep. 26, 2009
Application note OMAP-L137 Complementary Products Sep. 23, 2009
White paper Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core Jun. 24, 2009
Application note TMS320C6747/45/43 & OMAP-L1x7 USB Downstream Host Compliance Testing Mar. 12, 2009
Application note TMS320C6747/45/43 & OMAP-L1x7 USB Upstream Device Compliance Testing Mar. 12, 2009
Application note TMS320C674x/OMAP-L1x USB Compliance Checklist Mar. 12, 2009
Application note OMAP-L137 Technical Brief (Rev. B) Feb. 18, 2009
User guide TMS320C674x DSP Cache User's Guide (Rev. A) Feb. 11, 2009
User guide TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) May 15, 2008
User guide TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) May 15, 2008
User guide TMS320C6000 Assembly Language Tools v 6.0 Beta User's Guide (Rev. P) Oct. 31, 2006
User guide TMS320C6000 Optimizing Compiler v 6.0 Beta User's Guide (Rev. N) Jul. 29, 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
525
Description

The OMAP-L137/TMS320C6747 Floating-Point Starter Kit, developed jointly with Spectrum Digital Inc., is a low-cost development platform designed to speed the development of high-precision applications based on TI's OMAP-L13x applications processors and TMS320C674x fixed-/floating-point DSPs (...)

Features

Hardware - The Starter Kit (SK) features the OMAP-L137 applications processor that includes both a 300 MHz fixed/floating-point C674x DSP core and a 300 MHz ARM9 processor. This C674x DSP generation is designed for applications that require floating-point precision and fixed-point performance for (...)
DEBUG PROBE Download
XDS200 USB Debug Probe
TMDSEMU200-U
295
Description

The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)

Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBE Download
995
Description

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBE Download
1495
Description

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

Software development

SOFTWARE DEVELOPMENT KIT (SDK) Download
Processor SDK for OMAPL137 Processors TI-RTOS Support
PROCESSOR-SDK-OMAPL137 Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)
Features

RTOS Features:

  • Full driver availability
  • Debug and instrumentation utilities
  • Board support package
  • Demonstrations and examples
  • Code Composer Studio™ IDE for RTOS development
  • Documentation

The Processor SDK is free, and does not require any run-time royalties to Texas Instruments.

DRIVER OR LIBRARY Download
DSP Math Library for Floating Point Devices
MATHLIB — The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
Features
  • Types of functions included:
    • Trigonometric and hyperbolic: Sin, Cos, Tan, Arctan, etc.
    • Power, exponential, and logarithmic
    • Reciprocal
    • Square root
    • Division
  • Natural C Source Code
  • Optimized C code with Intrinsics
  • Hand-coded assembly-optimized routines
  • C-callable routines, which can be inlined and are fully (...)
DRIVER OR LIBRARY Download
TMS320C67x DSP Library
SPRC121 The TI C67x DSPLIB is an optimized floating-point DSP Function Library for C programmers using TMS320C67x devices. It includes C-callable, assembly-optimized general-purpose signal-processing routines. These routines are typically used in computationally intensive real-time applications where (...)
DRIVER OR LIBRARY Download
TMS320C5000/6000 Image Library (IMGLIB)
SPRC264 C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Image Analysis

  • Image boundry and perimeter
  • Morphological operation
  • Edge detection
  • Image Histogram
  • Image thresholding

Image filtering and format conversion

  • Color space conversion
  • Image convolution
  • Image correlation
  • Error diffusion
  • Median filtering
  • Pixel expansion

Image compression and decompression

  • Forward and (...)
DRIVER OR LIBRARY Download
TMS320C6000 DSP Library (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
DRIVER OR LIBRARY Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
DRIVER OR LIBRARY Download
Wind River Processors VxWorks and Linux operating systems
Provided by Wind River Systems Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
IDE, CONFIGURATION, COMPILER OR DEBUGGER Download
Code Composer Studio (CCS) Integrated Development Environment (IDE)
CCSTUDIO

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

OPERATING SYSTEM (OS) Download
Mentor Graphics Nucleus RTOS
Provided by Mentor Graphics Corporation — Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify application (...)
SOFTWARE CODEC Download
Adaptive Digital Technologies DSP VOIP, speech and audio codecs
Provided by Adaptive Digital Technologies, Inc. — Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide solutions (...)
SOFTWARE CODEC Download
Auro Technologies Auro-CODEC and Auro-Matic software
Provided by Auro Technologies N.V. — Auro Technologies’ Auro-Engine includes their Auro-Codec and Auro-Matic elements for real time audio stream encoding and up mixing affording 3D audio user experiences. The Auro-Codec and Auro-Matic algorithms have been ported to select TI C6x DSPs.
SOFTWARE CODEC Download
Vocal technologies DSP VoIP codecs
Provided by VOCAL Technologies, Ltd. — With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)

Design tools & simulation

SIMULATION MODEL Download
SPRM328B.ZIP (19 KB) - BSDL Model
SIMULATION MODEL Download
SPRM333A.ZIP (176 KB) - IBIS Model

Reference designs

REFERENCE DESIGNS Download
Powering the OMAP-L132/OMAP-L137/OMAP-L138 with the TPS650061
PR2084 — This reference design presents a complete power solution and low-cost, discrete sequencing circuit for the OMAP-L132, OMAP-L137, and OMAP-L138 processors.
Design files

CAD/CAE symbols

Package Pins Download
BGA (ZKB) 256 View options

Ordering & quality

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  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

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