Product details

Arm CPU 1 Arm Cortex-A8 Arm MHz (Max.) 720 CPU 32-bit Display type 1 LCD Operating system Linux, RTOS Rating Catalog Operating temperature range (C) -40 to 105, 0 to 90
Arm CPU 1 Arm Cortex-A8 Arm MHz (Max.) 720 CPU 32-bit Display type 1 LCD Operating system Linux, RTOS Rating Catalog Operating temperature range (C) -40 to 105, 0 to 90
FCCSP (CUS) 423 256 mm² 16 x 16 POP-FCBGA (CBB) 515 144 mm² 12 x 12
  • OMAP3 Devices:
    • OMAP™ 3 Architecture
    • MPU Subsystem
      • Up to 720-MHz ARM® Cortex™-A8 Core
      • NEON™ SIMD Coprocessor
    • PowerVR® SGX™ Graphics Accelerator
      • Tile-Based Architecture Delivering up to 1 MPoly/sec
      • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Programmable High-Quality Image Anti-Aliasing
    • Fully Software-Compatible with ARM9™
    • Commercial and Extended Temperature Grades
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • TrustZone®
      • Thumb®-2
      • MMU Enhancements
    • In-Order, Dual-Issue, Superscalar Microprocessor Core
    • NEON Multimedia Architecture
    • Over 2x Performance of ARMv6 SIMD
    • Supports Both Integer and Floating-Point SIMD
    • Jazelle® RCT Execution Environment Architecture
    • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
    • Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
  • ARM Cortex-A8 Memory Architecture:
    • -KB Instruction Cache (4-Way Set-Associative)
    • -KB Data Cache (4-Way Set-Associative)
    • -KB L2 Cache
  • 112KB of ROM
  • 64KB of Shared SRAM
  • Endianess:
    • ARM Instructions – Little Endian
    • ARM Data – Configurable
  • External Memory Interfaces:
    • General Purpose Memory Controller (GPMC)
      • 16-Bit-Wide Multiplexed Address and Data Bus
      • Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
      • Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
      • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
      • Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
  • System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
  • Camera Image Signal Processor (ISP)
    • CCD and CMOS Imager Interface
    • Memory Data Input
    • BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
    • Glueless Interface to Common Video Decoders
    • Resize Engine
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
  • Display Subsystem
    • Parallel Digital Output
      • Up to 24-Bit RGB
      • HD Maximum Resolution
      • Supports Up to 2 LCD Panels
      • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
    • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
      • Composite NTSC and PAL Video
      • Luma and Chroma Separate Video (S-Video)
    • Rotation 90-, 180-, and 270-Degrees
    • Resize Images From 1/4x to 8x
    • Color Space Converter
    • 8-Bit Alpha Blending
  • Serial Communication
    • 5 Multichannel Buffered Serial Ports (McBSPs)
      • 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
      • 5-KB Transmit and Receive Buffer (McBSP2)
      • SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
      • Direct Interface to I2S and PCM Device and TDM Buses
      • 128-Channel Transmit and Receive Mode
    • Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
    • High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
    • High-, Full-, and Low-Speed Multiport USB Host Subsystem
      • 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
    • One HDQ™/1-Wire® Interface
    • UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
    • Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • Removable Media Interfaces:
    • Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
  • Comprehensive Power, Reset, and Clock Management
    • SmartReflex™ Technology
    • Dynamic Voltage and Frequency Scaling (DVFS)
  • Test Interfaces
    • IEEE 1149.1 (JTAG) Boundary-Scan Compatible
    • ETM Interface
    • Serial Data Transport Interface (SDTI)
  • 12 32-Bit General-Purpose Timers
  • 2 32-Bit Watchdog Timers
  • 1 32-Bit 32-kHz Sync Timer
  • Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • 5-nm CMOS Technologies
  • Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
  • Discrete Memory Interface
  • Packages:
  • 1.8-V I/O and 3.0-V (MMC1 Only),


    Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.
  • OMAP3 Devices:
    • OMAP™ 3 Architecture
    • MPU Subsystem
      • Up to 720-MHz ARM® Cortex™-A8 Core
      • NEON™ SIMD Coprocessor
    • PowerVR® SGX™ Graphics Accelerator
      • Tile-Based Architecture Delivering up to 1 MPoly/sec
      • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Programmable High-Quality Image Anti-Aliasing
    • Fully Software-Compatible with ARM9™
    • Commercial and Extended Temperature Grades
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • TrustZone®
      • Thumb®-2
      • MMU Enhancements
    • In-Order, Dual-Issue, Superscalar Microprocessor Core
    • NEON Multimedia Architecture
    • Over 2x Performance of ARMv6 SIMD
    • Supports Both Integer and Floating-Point SIMD
    • Jazelle® RCT Execution Environment Architecture
    • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
    • Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
  • ARM Cortex-A8 Memory Architecture:
    • -KB Instruction Cache (4-Way Set-Associative)
    • -KB Data Cache (4-Way Set-Associative)
    • -KB L2 Cache
  • 112KB of ROM
  • 64KB of Shared SRAM
  • Endianess:
    • ARM Instructions – Little Endian
    • ARM Data – Configurable
  • External Memory Interfaces:
    • General Purpose Memory Controller (GPMC)
      • 16-Bit-Wide Multiplexed Address and Data Bus
      • Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
      • Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
      • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
      • Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
  • System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
  • Camera Image Signal Processor (ISP)
    • CCD and CMOS Imager Interface
    • Memory Data Input
    • BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
    • Glueless Interface to Common Video Decoders
    • Resize Engine
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
  • Display Subsystem
    • Parallel Digital Output
      • Up to 24-Bit RGB
      • HD Maximum Resolution
      • Supports Up to 2 LCD Panels
      • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
    • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
      • Composite NTSC and PAL Video
      • Luma and Chroma Separate Video (S-Video)
    • Rotation 90-, 180-, and 270-Degrees
    • Resize Images From 1/4x to 8x
    • Color Space Converter
    • 8-Bit Alpha Blending
  • Serial Communication
    • 5 Multichannel Buffered Serial Ports (McBSPs)
      • 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
      • 5-KB Transmit and Receive Buffer (McBSP2)
      • SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
      • Direct Interface to I2S and PCM Device and TDM Buses
      • 128-Channel Transmit and Receive Mode
    • Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
    • High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
    • High-, Full-, and Low-Speed Multiport USB Host Subsystem
      • 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
    • One HDQ™/1-Wire® Interface
    • UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
    • Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • Removable Media Interfaces:
    • Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
  • Comprehensive Power, Reset, and Clock Management
    • SmartReflex™ Technology
    • Dynamic Voltage and Frequency Scaling (DVFS)
  • Test Interfaces
    • IEEE 1149.1 (JTAG) Boundary-Scan Compatible
    • ETM Interface
    • Serial Data Transport Interface (SDTI)
  • 12 32-Bit General-Purpose Timers
  • 2 32-Bit Watchdog Timers
  • 1 32-Bit 32-kHz Sync Timer
  • Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • 5-nm CMOS Technologies
  • Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
  • Discrete Memory Interface
  • Packages:
  • 1.8-V I/O and 3.0-V (MMC1 Only),


    Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.

devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

  • Streaming video
  • Video conferencing
  • High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

  • Linux®
  • Windows® CE
  • Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

  • Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
  • PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP35 device only)
  • Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
  • Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
  • Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

  • A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
  • Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).

This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections:

  • Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
  • Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
  • Section 4: Clock Specifications input and output clocks, DPLL and DLL
  • Section 5: Video Dac Specifications
  • Section 6: Timing Requirements and Switching Characteristics
  • Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

  • Streaming video
  • Video conferencing
  • High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

  • Linux®
  • Windows® CE
  • Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

  • Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
  • PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP35 device only)
  • Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
  • Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
  • Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

  • A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
  • Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).

This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections:

  • Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
  • Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
  • Section 4: Clock Specifications input and output clocks, DPLL and DLL
  • Section 5: Video Dac Specifications
  • Section 6: Timing Requirements and Switching Characteristics
  • Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

Download

No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

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View all 22
Type Title Date
* Data sheet OMAP3515 and OMAP3503 Applications Processors datasheet (Rev. H) 10 Oct 2013
* Errata OMAP3530/25/15/03 Applications Processor Silicon Errata (Rev. F) 12 Oct 2010
* User guide OMAP35x Technical Reference Manual (Rev. Y) 19 Dec 2012
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 01 Jun 2020
Application note (Cancelled - see the B revision, create by mistake 14-may-2009) (Rev. C) PDF | HTML 03 Mar 2020
Application note OMAP3530/25/15/03, DM3730/25, AM3715/03 CBB, CBC and CUS reflow profiles 20 Mar 2019
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 24 Sep 2018
Technical article Difficult to see. Always in motion is the future 04 Jan 2016
Technical article Announcing the new entry-level Sitara processor 09 Dec 2015
Technical article Automotive Surround View Technology trends 31 Aug 2015
Technical article Where are DSPs used? What makes them so good at math? How do they work with Open APIs? 06 Aug 2015
Application note PCB Assembly Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part II (Rev. A) 01 Nov 2013
User guide Delta for OMAP35x Technical Reference Manual Version X to Version Y (Rev. Y) 10 Dec 2012
Application note PCB Assembly Guidelines for 0.5mm Package-on-Package Apps Processors, Part II 23 Jun 2010
Application note PCB Design Guidelines for 0.5mm Package-On-Package Apps Processors, Part I 23 Jun 2010
Application note Migrating from OMAP3530 to AM37x 03 Jun 2010
Application note Migrating from OMAP3530 to AM35x 24 May 2010
User guide OMAP35x Peripherals Overview Reference Guide (Rev. A) 20 Jan 2010
Application note OMAP35x Linux PSP Data Sheet 16 Oct 2009
Design guide Powering OMAP35x with TPS65073x 13 Oct 2009
Application note Powering OMAP™3 With TPS6235x: Design-In Guide 03 Dec 2008
Application note OMAP35x 0.65mm Pitch Layout Methods (Rev. B) 26 Jun 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

Not available on TI.com
Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Software codec

OMAP35XCODECS Codecs for OMAP35x - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
OMAP3503 Sitara processor: Arm Cortex-A8, LPDDR OMAP3515 Sitara Processor: Arm Cortex-A8, 3D Graphics, LPDDR OMAP3525 Applications Processor OMAP3530 Applications Processor
Download options
Software programming tool

FLASHTOOL FlashTool for AM35x, AM37x, DM37x and OMAP35x Devices

Flash Tool is a Windows-based application that can be used to transfer binary images from a host PC to TI Sitara AM35x, AM37x, DM37x and OMAP35x target platforms.


Additional Information:

TI GForge - Welcome to gforge.ti.com

TI E2E Community

Supported products & hardware

Supported products & hardware

Products
Arm-based processors
AM3505 Sitara processor: Arm Cortex-A8, video front end AM3517 Sitara processor: Arm Cortex-A8, 3D graphics, video front end AM3703 Sitara processor: Arm Cortex-A8, camera AM3715 Sitara processor: Arm Cortex-A8, 3D graphics, camera DM3725 Digital Media Processor DM3730 Digital Media Processor OMAP3503 Sitara processor: Arm Cortex-A8, LPDDR OMAP3515 Sitara Processor: Arm Cortex-A8, 3D Graphics, LPDDR OMAP3525 Applications Processor OMAP3530 Applications Processor
Download options
Software development kit (SDK)

ANDROIDSDK-SITARA — Android Development Kit for Sitara Microprocessors

Although originally designed for mobile handsets, the Android Operating System offers designers of embedded applications the ability to easily add a high-level OS to their product. Developed in association with Google, Android delivers a complete operating system  that is ready for (...)
Software development kit (SDK)

LINUXDVSDK-OMAP3530 — Linux Digital Video Software Development Kit (DVSDK) for OMAP3530/3525 Digital Media Processors

The Linux Digital Video Software Development Kit (DVSDK) enables OMAP35x system integrators to quickly develop Linux-based multimedia applications that can be easily ported across different devices in the OMAP35x generation, including OMAP3530 and OMAP3525 application processors. The DVSDK combines (...)
IDE, configuration, compiler or debugger

CCSTUDIO-SITARA — Code Composer Studio (CCS) Integrated Development Environment (IDE) for Sitara ARM Processors

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, (...)

Software codec

C64XPLUSCODECS — CODECS - Video and Speech- C64x+-based Devices (OMAP35x, C645x, C647x, DM646, DM644x, DM643x)

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes are on (...)
Simulation model

OMAP3515/03 CUS BSDL Model (Rev. B) OMAP3515/03 CUS BSDL Model (Rev. B)

Simulation model

OMAP3515/03 CBB BSDL Model (Rev. C) OMAP3515/03 CBB BSDL Model (Rev. C)

Simulation model

OMAP3515/03 CUS IBIS Model (Rev. B) OMAP3515/03 CUS IBIS Model (Rev. B)

Simulation model

OMAP3515/03 CBB IBIS Model (Rev. A) OMAP3515/03 CBB IBIS Model (Rev. A)

Simulation model

OMAP3515/03 CBC IBIS Model (Rev. A) OMAP3515/03 CBC IBIS Model (Rev. A)

Simulation model

OMAP3515/03 CBC BSDL MODEL OMAP3515/03 CBC BSDL MODEL

Calculation tool

POWEREST Power Estimation Tool (PET)

Power Estimation Tool (PET) provides users the ability to gain insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be (...)
Design tool

PROCESSORS-3P-SEARCH Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
Schematic

Schematic for PR785: Discrete Power Solution for OMAP3503 & OMAP3515 Schematic for PR785: Discrete Power Solution for OMAP3503 & OMAP3515

Package Pins Download
FCBGA (CUS) 423 View options
POP-FCBGA (CBB) 515 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

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