Product details


Function Mux buffer Protocols LVDS, LVPECL, CML, BLVDS Number of transmitters 2, 4 Number of receivers 2, 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal LVDS, LVPECL, CML, BLVDS Output signal LVCMOS, LVDS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

WQFN (RHS) 48 49 mm² 7 x 7 open-in-new Find other LVDS, M-LVDS & PECL ICs


  • 1.5 Gbps Data Rate Per Channel
  • Configurable Off/On Pre-emphasis Drives Lossy Backplanes and Cables
  • LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs
  • Low Output Skew and Jitter
  • On-chip 100Ω Input and Output Termination
  • IEEE 1149.1 and 1149.6 Compliant
  • 15 kV ESD Protection on LVDS Inputs/Outputs
  • Hot Plug Protection
  • Single 3.3V Supply
  • Industrial -40 to +85°C Temperature Range
  • 48-Pin WQFN Package

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The SCAN15MB200 is a dual-port 2 to 1 multiplexer and 1 to 2 repeater/buffer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs and outputs interface to LVDS or Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, or to CML or LVPECL signals.

Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports testability of both single-ended LVTTL/CMOS and high-speed differential PCB interconnects. The 3.3V supply, CMOS process, and robust I/O ensure high performance at low power over the entire industrial -40 to +85°C temperature range.

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Technical documentation

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Type Title Date
* Datasheet SCAN15MB200 Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer w/Pre-Emphasis & IEEE 1149.6 datasheet (Rev. E) Apr. 12, 2013

Design & development

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Design tools & simulation

SNLC059.ZIP (2 KB) - BSDL Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

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