Product details

Function Buffer Protocols LVDS, LVPECL, CML, BLVDS Number of transmitters 4 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (C) -40 to 85
Function Buffer Protocols LVDS, LVPECL, CML, BLVDS Number of transmitters 4 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (C) -40 to 85
TQFP (PFB) 48 81 mm² 9 x 9
  • 1.5 Gbps Maximum Data Rate Per Channel
  • Configurable Pre-emphasis Drives Lossy Backplanes and Cables
  • Low Output Skew and Jitter
  • LVDS/CML/LVPECL Compatible Input, LVDS Output
  • On-chip 100Ω Input and Output Termination
  • 12 kV ESD Protection on LVDS Outputs
  • IEEE 1149.1 JTAG Interface
  • IEEE 1149.6 Limited Capability
  • Fault Insertion
  • Single 3.3V Supply
  • Very Low Power Consumption
  • Industrial -40 to +85°C Temperature Range
  • Small TQFP Package Footprint
  • See DS90LV004 for Non-JTAG Version

All trademarks are the property of their respective owners.

  • 1.5 Gbps Maximum Data Rate Per Channel
  • Configurable Pre-emphasis Drives Lossy Backplanes and Cables
  • Low Output Skew and Jitter
  • LVDS/CML/LVPECL Compatible Input, LVDS Output
  • On-chip 100Ω Input and Output Termination
  • 12 kV ESD Protection on LVDS Outputs
  • IEEE 1149.1 JTAG Interface
  • IEEE 1149.6 Limited Capability
  • Fault Insertion
  • Single 3.3V Supply
  • Very Low Power Consumption
  • Industrial -40 to +85°C Temperature Range
  • Small TQFP Package Footprint
  • See DS90LV004 for Non-JTAG Version

All trademarks are the property of their respective owners.

The SCAN90004 is a four channel 1.5 Gbps LVDS buffer/repeater. High speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while configurable pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs and outputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. The repeater function is especially useful for boosting signals for longer distance transmission over lossy cables and backplanes.

Integrated testability circuitry supports IEEE1149.1 (JTAG) on single-ended LVTTL/CMOS I/O and limited IEEE1149.6 capability on high-speed differential LVDS interconnects. The 3.3V supply, CMOS process, and LVDS I/O ensure stable high performance at low power over the entire industrial -40 to +85°C temperature range.

The SCAN90004 is a four channel 1.5 Gbps LVDS buffer/repeater. High speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while configurable pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs and outputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. The repeater function is especially useful for boosting signals for longer distance transmission over lossy cables and backplanes.

Integrated testability circuitry supports IEEE1149.1 (JTAG) on single-ended LVTTL/CMOS I/O and limited IEEE1149.6 capability on high-speed differential LVDS interconnects. The 3.3V supply, CMOS process, and LVDS I/O ensure stable high performance at low power over the entire industrial -40 to +85°C temperature range.

Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet SCAN90004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis datasheet (Rev. P) 12 Apr 2013
Application note Signaling Rate vs. Distance for Differential Buffers 26 Jan 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Package Pins Download
TQFP (PFB) 48 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos