Product details

Function Transceiver Protocols JTAG IEEE1149.1, BLVDS Number of transmitters 9 Number of receivers 9 Supply voltage (V) 3.3 Signaling rate (Mbps) 100 Input signal LVDS, BLVDS, LVTTL, LVCMOS Output signal BLVDS Rating Catalog Operating temperature range (C) -40 to 85
Function Transceiver Protocols JTAG IEEE1149.1, BLVDS Number of transmitters 9 Number of receivers 9 Supply voltage (V) 3.3 Signaling rate (Mbps) 100 Input signal LVDS, BLVDS, LVTTL, LVCMOS Output signal BLVDS Rating Catalog Operating temperature range (C) -40 to 85
LQFP (PM) 64 100 mm² 10 x 10 NFBGA (NZC) 64 64 mm² 8 x 8
  • IEEE 1149.1 (JTAG) Compliant
  • Bus LVDS Signaling
  • Low Power CMOS Design
  • High Signaling Rate Capability (Above 100 Mbps)
  • 0.1V to 2.3V Common Mode Range for VID = 200mV
  • ±100 mV Receiver Sensitivity
  • Supports Open and Terminated Failsafe on Port Pins
  • 3.3V Operation
  • Glitch Free Power Up/Down (Driver & Receiver Disabled)
  • Light Bus Loading (5 pF Typical) per Bus LVDS Load
  • Designed for Double Termination Applications
  • Balanced Output Impedance
  • Product Offered in 64 Pin LQFP Package and NFBGA Package
  • High Impedance Bus Pins on Power Off (VCC = 0V)

All trademarks are the property of their respective owners.

  • IEEE 1149.1 (JTAG) Compliant
  • Bus LVDS Signaling
  • Low Power CMOS Design
  • High Signaling Rate Capability (Above 100 Mbps)
  • 0.1V to 2.3V Common Mode Range for VID = 200mV
  • ±100 mV Receiver Sensitivity
  • Supports Open and Terminated Failsafe on Port Pins
  • 3.3V Operation
  • Glitch Free Power Up/Down (Driver & Receiver Disabled)
  • Light Bus Loading (5 pF Typical) per Bus LVDS Load
  • Designed for Double Termination Applications
  • Balanced Output Impedance
  • Product Offered in 64 Pin LQFP Package and NFBGA Package
  • High Impedance Bus Pins on Power Off (VCC = 0V)

All trademarks are the property of their respective owners.

The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.

The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V.

The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels.

This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST).

The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.

The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V.

The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels.

This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST).

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* Data sheet SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN datasheet (Rev. I) 12 Apr 2013

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LQFP (PM) 64 View options
NFBGA (NZC) 64 View options

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