Packaging information
| Package | Pins CDIP (JT) | 28 |
| Operating temperature range (°C) -55 to 125 |
| Package qty | Carrier 13 | TUBE |
Features for the SN54ABT8652
- Members of the Texas Instruments SCOPETM Family of Testability Products
- Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
- Functionally Equivalent to 'F652 and 'ABT652 in the Normal-Function Mode
- SCOPETM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
- Parallel-Signature Analysis at Inputs With Masking Option
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Even-Parity Opcodes
- Two Boundary-Scan Cells Per I/O for Greater Flexibility
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- Package Options Include Shrink Small-Outline (DL) and Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)
SCOPE and EPIC-IIB are trademarks of Texas Instruments
Incorporated.
Description for the SN54ABT8652
The 'ABT8652 scan test devices with octal bus transceivers and registers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F652 and 'ABT652 octal bus transceivers and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal bus transceivers and registers.
Data flow in each direction is controlled by clock (CLKAB and
CLKBA), select (SAB and SBA), and output-enable (OEAB and 
) inputs. For A-to-B data flow,
data on the A bus is clocked into the associated registers on the
low-to-high transition of CLKAB. When SAB is low, real-time A data is
selected for presentation to the B bus (transparent mode). When SAB
is high, stored A data is selected for presentation to the B bus
(registered mode). When OEAB is high, the B outputs are active. When
OEAB is low, the B outputs are in the high-impedance state. Control
for B-to-A data flow is similar to that for A-to-B data flow but uses
CLKBA, SBA, and inputs. Since
the input is
active low, the A outputs are active when is low and are in the
high-impedance state when is
high. Figure 1 shows the four fundamental bus-management functions
that can be performed with the 'ABT8652.
In the test mode, the normal operation of the SCOPETM bus transceivers and registers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54ABT8652 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8652 is characterized for operation from -40°C to 85°C.