SN54ALS109A

ACTIVE

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset

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Product details

Parameters

Channels (#) 2 Technology Family ALS VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL Output type TTL Clock Frequency (MHz) 34 ICC (Max) (uA) 4000 IOL (Max) (mA) -0.4 IOH (Max) (mA) 8 Features Positive edge triggered, High speed (tpd 10-50ns), Preset, Clear open-in-new Find other J-K flip-flop

Package | Pins | Size

CDIP (J) 16 135 mm² 19.65 x 6.92 LCCC (FK) 20 79 mm² 8.89 x 8.89 open-in-new Find other J-K flip-flop

Features

  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

 

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Description

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.

 

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset datasheet (Rev. B) Aug. 01, 1995
* SMD SN54ALS109A SMD 84000012A Jun. 21, 2016
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

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CAD/CAE symbols

Package Pins Download
CDIP (J) 16 View options
LCCC (FK) 20 View options

Ordering & quality

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