SN54AS175B

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Hex/Quadruple D-type Flip-Flops With Clear

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Product details

Parameters

Channels (#) 4 Technology Family AS VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type Bipolar Output type Push-Pull Clock Frequency (Max) (MHz) 100 IOL (Max) (mA) 20 IOH (Max) (mA) -2 ICC (Max) (uA) 34000 Features Very high speed (tpd 5-10ns) open-in-new Find other D-type flip-flop

Package | Pins | Size

CDIP (J) 16 135 mm² 19.65 x 6.92 open-in-new Find other D-type flip-flop

Features

  • ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs
  • ’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail Outputs
  • Buffered Clock and Direct-Clear Inputs
  • Applications Include:
    • Buffer/Storage Registers
    • Shift Registers
    • Pattern Generators
  • Fully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

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Description

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

These circuits are fully compatible for use with most TTL circuits.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Hex/Quadruple D-Type Flip-Flops With Clear datasheet (Rev. E) May 23, 2002
* SMD SN54AS175B SMD 5962-95537 Jun. 21, 2016
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Advanced Schottky Load Management Feb. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Application note Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

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CAD/CAE symbols

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CDIP (J) 16 View options

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