Product details

Number of channels 8 Technology family BCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 48 IOH (max) (mA) -12 Supply current (max) (µA) 60000 Features Ultra high speed (tpd <5ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 8 Technology family BCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 48 IOH (max) (mA) -12 Supply current (max) (µA) 60000 Features Ultra high speed (tpd <5ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 20 167.464 mm² 24.2 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Operating Voltage Range of 4.5 V to 5.5 V
  • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
  • Full Parallel Access for Loading
  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)

  • Operating Voltage Range of 4.5 V to 5.5 V
  • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
  • Full Parallel Access for Loading
  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’BCT373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’BCT373 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

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Technical documentation

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Type Title Date
* Data sheet SN54BCT373, SN74BCT373 datasheet (Rev. D) 11 Mar 2003
* SMD SN54BCT373 SMD 5962-90746 21 Jun 2016
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996

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CDIP (J) 20 Ultra Librarian
LCCC (FK) 20 Ultra Librarian

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