SN54HC112

ACTIVE

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset

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Product details

Parameters

Bits (#) 2 Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Input type CMOS Output type CMOS ICC @ nom voltage (Max) (mA) 0.04 IOL (Max) (mA) -4 open-in-new Find other J-K flip-flop

Package | Pins | Size

CDIP (J) 16 CFP (W) 16 LCCC (FK) 20 open-in-new Find other J-K flip-flop

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 40-µA Max ICC
  • Typical tpd = 13 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max

open-in-new Find other J-K flip-flop

Description

The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When (PRE)\ and (CLR)\ are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops by tying J and K high.

open-in-new Find other J-K flip-flop
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN54HC112, SN74HC112 datasheet (Rev. F) Sep. 26, 2003
* SMD SN54HC112 SMD 84088012A Jun. 21, 2016
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
CDIP (J) 16 View options
CFP (W) 16 View options
LCCC (FK) 20 View options

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