SN54HC573A-SP

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Product details

Number of channels (#) 8 Technology Family HC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Input type Standard CMOS Output type 3-State Clock Frequency (Max) (MHz) 28 IOL (Max) (mA) 7.8 IOH (Max) (mA) -7.8 ICC (Max) (uA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Flow-through pinout
Number of channels (#) 8 Technology Family HC Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 6 Input type Standard CMOS Output type 3-State Clock Frequency (Max) (MHz) 28 IOL (Max) (mA) 7.8 IOH (Max) (mA) -7.8 ICC (Max) (uA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Flow-through pinout
CDIP (J) 20 167 mm² 26.92 x 7.62
  • Wide Operating Voltage Range from 2 V to 6 V
  • High-Current 3-State Outputs Drive Bus Lines Directly up to 15 LSTTL Loads
  • Low Power Consumption: 80-µA Maximum ICC
  • Typical tpd = 21 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current: 1 µA (Maximum)
  • Bus-Structured Pinout
  • Wide Operating Voltage Range from 2 V to 6 V
  • High-Current 3-State Outputs Drive Bus Lines Directly up to 15 LSTTL Loads
  • Low Power Consumption: 80-µA Maximum ICC
  • Typical tpd = 21 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current: 1 µA (Maximum)
  • Bus-Structured Pinout

The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.

The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.

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Technical documentation

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Type Title Date
* Data sheet SNx4HC573A Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. G) 20 Apr 2022
* SMD SN54HC573A-SP SMD 5962-85128 08 Jul 2016
Selection guide TI Space Products (Rev. I) 03 Mar 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations 18 May 2020
Application note Single-Event Effects Confidence Interval Calculations 14 Jan 2020
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing 17 Jun 2019
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) 06 Feb 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

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