4-Bit Parallel-Access Shift Registers


Product details


Technology Family LS VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL Output type TTL IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 open-in-new Find other Shift register

Package | Pins | Size

CDIP (J) 16 135 mm² 19.65 x 6.92 LCCC (FK) 20 79 mm² 8.89 x 8.89 open-in-new Find other Shift register


  • Synchronous Parallel Load
  • Positive-Edge-Triggered Clocking
  • Parallel Inputs and Outputs from Each Flip-Flop
  • Direct Overriding Clear
  • J and K\ Inputs to First Stage
  • Complementary Outputs from Last Stage
  • For Use in High Performance:
    • Accumulators/Processors
    • Serial-to-Parallel, Parallel-to-Serial Converters


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These 4-bit registers feature parallel inputs, parallel outputs, J-K\ serial inputs, shift/load (SH/LD\) control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The register has two modes of operation:

Parallel (broadside) loadShift (in the direction QA toward QD)

Parallel loading is accomplished by applying the four bits of data and taking SH/LD\ low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when SH/LD\ is high. Serial data for this mode is entered at the J-K\ inputs. These inputs permit the first stage to perform as a J-K\, D-, or T-type flip-flop as shown in the function table.

The high-performance 'S195, with a 105-megahertz typical maximum shift-frequency, is particularly attractive for very-high-speed data processing systems. In most cases existing systems can be upgraded merely by using this Schottky-clamped shift register.


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Technical documentation

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Type Title Date
* Datasheet 4-Bit Parallel-Access Shift Registers datasheet Mar. 01, 1988
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
CDIP (J) 16 View options
LCCC (FK) 20 View options

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