SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) bridge features a
dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at
1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp
RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with
up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4
The SN65DSI86-Q1 is
well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 ×
1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented
to accommodate the data stream mismatch between the DSI and DisplayPort
Designed with industry compliant interface technology, the is compatible with a wide range of microprocessors, and is
designed with a range of power management features, including panel refresh support, and the MIPI
defined ultralow power state (ULPS) support.
The SN65DSI86 Q1 is implemented in a 10-mm × 10-mm
HTQFP at 0.5-mm pitch package, and operates across a temperature range from –40°C to +85°C.
In the rest of this document, the SN65DSI86-Q1 is referred to as SN65DSIx6 or DSIx6.