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Product details

Parameters

Function Receiver, Translator Protocols PECL Number of transmitters 0 Number of receivers 2 Supply voltage (V) 5 Signaling rate (Mbps) 500 Input signal PECL Output signal TTL Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 8 19 mm² 3.91 x 4.9 VSSOP (DGK) 8 15 mm² 3 x 4.9 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • Dual 5-V Differential PECL-to-TTL Buffer
  • 24-mA TTL Ouputs
  • Operating Range
    • PECL VCC = 4.75 V to 5.25 V with GND = 0 V
  • Support for Clock Frequencies of 250 MHz (TYP)
  • 3.5-ns Typical Propagation Delay
  • Output Default Low with Inputs Left Open or <1.3 V
  • Internal Input 50-k Pull-Down Resistor
  • Built-In Temperature Compensation
  • Drop-In Compatible to the MC100ELT23
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data

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Description

The SN65ELT23 is a low power dual PECL-to-TTL translator device. The device includes circuitry to maintain a known logic low level when inputs are in an open condition. The SN65ELT23 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.

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Technical documentation

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Type Title Date
* Data sheet 5-V Dual Differential PECL Buffer-to-TTL Translator datasheet Jun. 30, 2009
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct. 17, 2007

Design & development

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CAD/CAE symbols

Package Pins Download
SOIC (D) 8 View options
VSSOP (DGK) 8 View options

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