CAN Transceiver with Fast Loop Times for Highly Loaded Networks
Product details
Parameters
Package | Pins | Size
Features
- Meets the Requirements of ISO11898-2
- Turbo CAN:
- Short and Symmetrical Propagation Delay
Times and Fast Loop Times for Enhanced
Timing Margin - Higher Data Rates in CAN Networks
- Short and Symmetrical Propagation Delay
- I/O Voltage Range Supports 3.3-V and 5-V MCUs
- Ideal Passive Behavior When Unpowered
- Bus and Logic Pins are High Impedance (No
Load) - Power Up and Power Down With Glitch-Free
Operation on Bus
- Bus and Logic Pins are High Impedance (No
- Protection Features
- HBM ESD Protection Exceeds ±12 kV
- Bus Fault Protection –27 V to 40 V
- Undervoltage Protection on Supply Pins
- Driver Dominant Time Out (TXD DTO)
- SN65HVD257: Receiver-Dominant Time Out
(RXD DTO) - SN65HVD257: FAULT Output Pin
- Thermal Shutdown Protection
- Characterized for –40°C to 125°C Operation
Description
This CAN transceiver meets the ISO1189-2 High Speed CAN (Controller Area Network) Physical Layer standard. It is designed for data rates in excess of 1 Mbps for CAN in short networks, and enhanced timing margin and higher data rates in long and highly-loaded networks. The device provides many protection features to enhance device and CAN-network robustness. The SN65HVD257 device adds additional features, allowing for easy design of redundant and multitopology networks with fault indication for higher levels of functional safety in the CAN system.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | SN65HVD25x Turbo CAN Transceivers for Higher Data Rates and Large Networks Including Features for Functional Safety datasheet (Rev. D) | May 09, 2015 |
Application note | CAN and LIN transceiver low-power modes | Feb. 25, 2019 | |
Technical article | The need for even more speed: CAN FD | Apr. 11, 2014 | |
User guide | CAN EVM User's Guide | Oct. 14, 2011 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download TIDA-00267 Gerber.zip (236KB) -
download TIDA-00267 BOM (Rev. A).pdf (113KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (D) | 8 | View options |
Ordering & quality
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- Material content
- Qualification summary
- Ongoing reliability monitoring
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