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Quad LVDS receiver with flow-through pinout

SN65LVDS048A

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Product details

Parameters

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal LVDS Output signal TTL, LVTTL Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

SOIC (D) 16 59 mm² 9.9 x 6 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other LVDS, M-LVDS & PECL ICs

Features

  • >400 Mbps (200 MHz) Signaling Rates
  • Flow-Through Pinout Simplifies PCB Layout
  • 50 ps Channel-to-Channel Skew (Typ)
  • 200 ps Differential Skew (Typ)
  • Propagation Delay Times 2.7 ns (Typ)
  • 3.3-V Power Supply Design
  • High Impedance LVDS Inputs on Power Down
  • Low-Power Dissipation (40 mW at 3.3 V Static)
  • Accepts Small Swing (350 mV) Differential Signal Levels
  • Supports Open, Short, and Terminated Input Fail-Safe
  • Industrial Operating Temperature Range (–40°C to 85°C)
  • Conforms to TIA/EIA-644 LVDS Standard
  • Available in SOIC and TSSOP Packages
  • Pin-Compatible With DS90LV048A From National

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Description

The SN65LVDS048A is a quad differential line receiver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the quad differential receivers will provide a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

The SN65LVDS048A is characterized for operation from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet LVDS Quad Differential Line Receiver datasheet (Rev. B) Sep. 03, 2002
Application note Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. A) Jun. 01, 2020
Application note LVDS to Improve EMC in Motor Drives Sep. 27, 2018
Application note How Far, How Fast Can You Operate LVDS Drivers and Receivers? Aug. 03, 2018
Application note How to Terminate LVDS Connections with DC and AC Coupling May 16, 2018

Design & development

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Design tools & simulation

SIMULATION MODEL Download
SLLC048A.ZIP (4 KB) - IBIS Model
SIMULATION MODEL Download
SLLC213.ZIP (4 KB) - IBIS Model
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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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CAD/CAE symbols

Package Pins Download
SOIC (D) 16 View options
TSSOP (PW) 16 View options

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