Product details


Function Serializer Protocols Channel-Link I Supply voltage (V) 1.8 Signaling rate (Mbps) 1755 Input signal CMOS Output signal LVDS Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other LVDS, M-LVDS & PECL ICs

Package | Pins | Size

DSBGA (YFF) 49 0 mm² 2.8 x 2.8 open-in-new Find other LVDS, M-LVDS & PECL ICs


  • 2.8 × 2.8mm package size
  • 1.8V input signal swing
  • 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit and 2 Reserved Bits
    Transmitted over 1, 2 or 3 Differential Lines
  • SubLVDS Differential Voltage Levels
  • Three Operating Modes to Conserve Power
    • Active-Mode QVGA 17.4mW (typ)
    • Active-Mode VGA 28.8mW (typ)
    • Shutdown Mode ≈ 0.5µA (typ)
    • Standby Mode ≈ 0.5µA (typ)
  • ESD Rating > 3kV (HBM)
  • Pixel Clock Range of 4MHz–65MHz
  • Failsafe on all CMOS Inputs
  • Typical Application: Cameras, Embedded Computers

open-in-new Find other LVDS, M-LVDS & PECL ICs


The SN65LVDS311 serializer transmits 27 parallel input data over 1, 2, or 3 serial output links. The device pinout is optimized to interface with the OMAP3630 application processor. The device loads a shift register with the 24 pixel bits and 3 control bits from the parallel CMOS input interface. The data are latched into the device by the pixel clock, PCLK. In addition to the 27 bits, the device adds a parity bit and two reserved bits for a total number of 30 serial bits. The parity bit allows a receiver to detect single-bit errors. Odd parity is implemented.

The serial shift register is uploaded through 1, 2, or 3 serial outputs at 30, 15, or 10 times the pixel clock data rate. A copy of the pixel clock is output on an additional differential output. The serial data and clock are transmitted via Sub Low-Voltage Differential Signaling (SubLVDS) lines. The SN65LVDS311 supports three power modes (Shutdown, Standby and Active) to conserve power.

When transmitting, the PLL locks to the incoming pixel clock PCLK and generates an internal high-speed clock at the line rate of the data lines. The parallel data is latched on the rising edge of PCLK. The serialized data is presented on the serial outputs D0, D1, D2 with a recreation of the Pixel clock PCLK generated from the internal high-speed clock and output on the CLK output. If the input clock PCLK stops, the device enters a standby mode to conserve power.

Two Link-Select lines LS0 and LS1 control whether 1, 2 or 3 serial links are used. The TXEN input may be used to put the SN65LVDS311 in a shutdown mode. The SN65LVDS311 enters an active Standby mode if the input clock PCLK stops. This minimizes power consumption without the need for controlling an external pin. The SN65LVDS311 is characterized for operation over ambient air temperatures of -40°C to 85°C. All CMOS inputs offer failsafe to protect the input from damage during power-up and to avoid current flow into the device inputs during power-up.

open-in-new Find other LVDS, M-LVDS & PECL ICs

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet SN65LVDS311 Programmable 27 Bit Display Serial Interface Transmitter datasheet (Rev. B) Mar. 22, 2013

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
DSBGA (YFF) 49 View options

Ordering & quality

Information included:
  • RoHS
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​