The SN65LVDS93A LVDS SerDes (serializer/deserializer) transmitter contains four 7-bit
parallel load serial-out shift registers, a 7 × clock synthesizer, and five low-voltage
differential signaling (LVDS) drivers in a single integrated circuit. These functions allow
synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors
for receipt by a compatible receiver, such as the SN65LVDS94 (SLLS928).
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge
of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected through
the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to
serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked
clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the
input clock, CLKIN.
The SN65LVDS93A device requires no external components and little or no control. The data
bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the users. The only user intervention is selecting a clock rising edge
by inputting a high level to CLKSEL or a falling edge with a low-level input and the possible use
of the shutdown/clear (SHTDN) signal. SHTDN is an active-low input to inhibit the clock and shut
off the LVDS output drivers for lower power consumption. A low level on this signal clears all
internal registers at a low level.
The SN65LVDS93A is characterized for operation over ambient air temperatures of 40°C to