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Product details

Parameters

Function Serializer Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Display SerDes

Package | Pins | Size

TSSOP (DGG) 56 113 mm² 14 x 8.1 open-in-new Find other Display SerDes

Features

  • Industrial Temperature Range –40°C to 85°C
  • LVDS Display Serdes Interfaces Directly to LCD Display Panels With Integrated LVDS
  • Package Options: 8.1-mm × 14-mm TSSOP
  • 1.8 V up to 3.3-V Tolerant Data Inputs to Connect Directly to Low-Power, Low-Voltage Application and Graphic Processors
  • Transfer Rate up to 85 Mpps (Mega Pixels Per Second); Pixel Clock Frequency Range 10 MHz to 85 MHz; Max 2.38 Gbps data rate supported
  • Suited for Display Resolutions Ranging From HVGA up to HD With Low EMI
  • Operates From a Single 3.3-V Supply and 170 mW (Typical) at 75 MHz
  • 28 Data Channels Plus Clock In Low-Voltage TTL to 4 Data Channels Plus Clock Out Low-Voltage Differential
  • Consumes Less Than 1 mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered Inputs
  • ESD: 5-kV HBM
  • Supports Spread Spectrum Clocking (SSC)
  • Supports RGB 888 to LVDS I Conversion

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Description

The SN65LVDS93B LVDS SerDes (serializer/deserializer) transmitter contains four 7-bit parallel load serial-out shift registers, a 7 × clock synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These functions allow synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors for receipt by a compatible receiver, such as the DS90CR286A and SN65LVDS94.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected through the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN65LVDS93B device requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the users. The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input and the possible use of the shutdown/clear (SHTDN) signal. SHTDN is an active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers at a low level.

The SN65LVDS93B is characterized for operation over ambient air temperatures of –40°C to 85°C.

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Technical documentation

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Type Title Date
* Datasheet SN65LVDS93B 10 MHz - 85 MHz 28-bit Flat Panel Display Link LVDS Serdes Transmitter datasheet (Rev. A) May 15, 2018
Application notes High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs Nov. 09, 2018
Technical articles How to select serializers and deserializers in HMI systems Apr. 24, 2018
User guides LVDS83BTSSOPEVM User's Guide Oct. 13, 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$599.00
Description
The SN75LVDS83B transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted (...)
Features
  • Plug and play design
  • Power the EVM by USB VBUS or 5- to 5.5-V DC IN through a power jack J3
  • Access the I2C bus through headers
  • Configurable through dip Switches

Design tools & simulation

SIMULATION TOOLS Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

Reference designs

REFERENCE DESIGNS Download
RGB to OLDI/LVDS Display Bridge Reference Design for Sitara™ Processors
TIDA-010013 — Higher resolution displays are now in larger demand than ever before. This results in a higher pixel clock which can lead to challenges such as high EMI emission and noise immunity. As a result, the video interface now transitions from a traditional RGB to LVDS video interface. As microprocessors (...)
document-generic Schematic document-generic User guide

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TSSOP (DGG) 56 View options

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