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SN65LVEP11

ACTIVE

PECL/ECL 1:2 fanout buffer

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Data sheet

SN65LVEP11

ACTIVE
Data sheet Order now

Product details

Function Translator Protocols ECL, PECL Number of transmitters 2 Number of receivers 1 Signaling rate (Mbps) 6000 Input signal ECL, PECL Output signal ECL, PECL Rating Catalog Operating temperature range (°C) -40 to 85
Function Translator Protocols ECL, PECL Number of transmitters 2 Number of receivers 1 Signaling rate (Mbps) 6000 Input signal ECL, PECL Output signal ECL, PECL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) VSSOP (DGK) 8 14.7 mm² (3 mm × 4.9 mm)
  • 1:2 PECL/ECL Fanout Buffer
  • Operating Range
    • PECL: VCC = 2.375 V to 3.8V With VEE = 0 V
    • NECL: VCC = 0 V With VEE = -2.375V to
      -3.8 V
  • Open Input Default State
  • Support for Clock Frequencies > 3.0 GHz
  • 240 ps Typical Propagation Delay
  • Deterministic Output Value for Open Input Conditions
  • Q Output Will Default Low When Input Open or at VEE
  • Built-in Temperature Compensation
  • Drop in Compatible to MC10LVEP11, MC100LVEP11
  • LVDS Input Compatible
  • 1:2 PECL/ECL Fanout Buffer
  • Operating Range
    • PECL: VCC = 2.375 V to 3.8V With VEE = 0 V
    • NECL: VCC = 0 V With VEE = -2.375V to
      -3.8 V
  • Open Input Default State
  • Support for Clock Frequencies > 3.0 GHz
  • 240 ps Typical Propagation Delay
  • Deterministic Output Value for Open Input Conditions
  • Q Output Will Default Low When Input Open or at VEE
  • Built-in Temperature Compensation
  • Drop in Compatible to MC10LVEP11, MC100LVEP11
  • LVDS Input Compatible

The SN65LVEP11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain known logic levels when the inputs are in an open condition. Single-ended clock input operation is limited to VCC ≥ 3 V in PECL mode, or VEE ≤ 3 V in NECL mode. The device is housed in an industry-standard SOIC-8 package and is also available in TSSOP-8 package option.

The SN65LVEP11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain known logic levels when the inputs are in an open condition. Single-ended clock input operation is limited to VCC ≥ 3 V in PECL mode, or VEE ≤ 3 V in NECL mode. The device is housed in an industry-standard SOIC-8 package and is also available in TSSOP-8 package option.
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* Data sheet 2.5V/3.3V PECL/ECL 1:2 Fanout Buffer datasheet (Rev. A) Dec 8, 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

SN65LVEP11 IBIS Model Version 1.3 (Rev. A)

SLLM046 (23 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian
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