SN74ACT74

ACTIVE

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

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Product details

Parameters

Number of channels (#) 2 Technology Family ACT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 90 IOL (Max) (mA) 24 IOH (Max) (mA) -24 ICC (Max) (uA) 20 Features Balanced outputs, Very high speed (tpd 5-10ns), Positive input clamp diode open-in-new Find other D-type flip-flop

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other D-type flip-flop

Features

  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 10.5 ns at 5 V
  • Inputs Are TTL-Voltage Compatible

open-in-new Find other D-type flip-flop

Description

The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE)\ or clear (CLR)\ input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

open-in-new Find other D-type flip-flop
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Technical documentation

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Type Title Date
* Data sheet SN54ACT74, SN74ACT74 datasheet (Rev. H) Oct. 23, 2003
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) Jul. 26, 2021
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

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