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SN74AHC595

ACTIVE

Eight-bit shift registers with tri-state output registers

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Data sheet

SN74AHC595

ACTIVE
Data sheet Order now

Product details

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family AHC Input type Standard CMOS Output type 3-State Clock frequency (MHz) 115 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Output register, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family AHC Input type Standard CMOS Output type 3-State Clock frequency (MHz) 115 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Output register, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 125 Rating Catalog
SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SSOP (DB) 16 48.36 mm² (6.2 mm × 7.8 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm) WQFN (BQB) 16 8.75 mm² (3.5 mm × 2.5 mm)
  • Operating range: 2V to 5.5V VCC
  • 8-bit serial-in, parallel-out shift
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
    • 1000V charged-device model (C101)
  • Operating range: 2V to 5.5V VCC
  • 8-bit serial-in, parallel-out shift
  • Latch-up performance exceeds 100mA per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000V human-body model (A114-A)
    • 1000V charged-device model (C101)

The SN74AHC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear ( SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except QH′ are in the high-impedance state.

The SN74AHC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear ( SRCLR) input, a serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except QH′ are in the high-impedance state.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74AHC595 8-Bit Shift Registers With 3-State Output Registers datasheet (Rev. N) PDF | HTML Jul 12, 2024
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

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SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
SSOP (DB) 16 Ultra Librarian
PDIP (N) 16 Ultra Librarian
WQFN (BQB) 16 Ultra Librarian
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