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The SN74AHCT74Q is a dual positive-edge-triggered D-type flip-flop.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. B) | Apr 24, 2008 | |
| Application note | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | Dec 15, 2022 | |
| More literature | Automotive Logic Devices Brochure | Aug 27, 2014 |
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The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (D) | 14 | Ultra Librarian |
| TSSOP (PW) | 14 | Ultra Librarian |
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