These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear (
) inputs sets or resets the outputs regardless of the levels of the other inputs. When
and
are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.
Part number | Order | Technology Family | Input type | Output type | VCC (Min) (V) | VCC (Max) (V) | Channels (#) | Clock Frequency (Max) (MHz) | ICC (uA) | IOL (Max) (mA) | IOH (Max) (mA) | Features | Rating | Package Group |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SN74ALS74A |
|
ALS | Bipolar | Push-Pull | 4.5 | 5.5 | 2 | 70 | 4000 | 8 | -0.4 | High speed (tpd 10-50ns) | Catalog |
PDIP | 14
SOIC | 14 SO | 14 |
SN54ALS74A | Samples not available | ALS | Bipolar | Push-Pull | 4.5 | 5.5 | 2 | 75 | 4000 | 8 | -0.4 | High speed (tpd 10-50ns) | Military |
CDIP | 14
CFP | 14 LCCC | 20 |